[coreboot-gerrit] Patch set updated for coreboot: soc/intel/common: Add bootblock common stage file [WIP]

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18457

-gerrit

commit 56fec38ba3a30c4b7b19400962bbe004dd77f858
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Tue Feb 21 18:25:30 2017 +0530

    soc/intel/common: Add bootblock common stage file [WIP]
    
    Currently added till bootblock_systemagent_early_init and
    expectation to reach post code 0x2b.
    
    Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
 src/soc/intel/common/Makefile.inc                 |  1 +
 src/soc/intel/common/basecode/Kconfig             |  4 ++
 src/soc/intel/common/basecode/Makefile.inc        |  5 +++
 src/soc/intel/common/basecode/bootblock.c         | 52 +++++++++++++++++++++++
 src/soc/intel/common/basecode/include/bootblock.h | 40 +++++++++++++++++
 5 files changed, 102 insertions(+)

diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 675b9b5..12b310e 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -36,6 +36,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c
 
 smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c
 
+CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include/
 CPPFLAGS_common += -I$(src)/soc/intel/common/block/include
 
 # Create and add the MRC cache to the cbfs image
diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig
new file mode 100644
index 0000000..24cd7a3
--- /dev/null
+++ b/src/soc/intel/common/basecode/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_BASECODE
+	bool
+	help
+	  Base code driver for non IP code
diff --git a/src/soc/intel/common/basecode/Makefile.inc b/src/soc/intel/common/basecode/Makefile.inc
new file mode 100644
index 0000000..074c782
--- /dev/null
+++ b/src/soc/intel/common/basecode/Makefile.inc
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_SOC_INTEL_BASECODE),y)
+
+bootblock-y += bootblock.c
+
+endif
diff --git a/src/soc/intel/common/basecode/bootblock.c b/src/soc/intel/common/basecode/bootblock.c
new file mode 100644
index 0000000..6deac95
--- /dev/null
+++ b/src/soc/intel/common/basecode/bootblock.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation..
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <bootblock.h>
+
+void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
+{
+	/* Call lib/bootblock.c main */
+	bootblock_main_with_timestamp(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+	bootblock_systemagent_early_init();
+	/* TODO: Add PCH and CPU driver
+	bootblock_pch_early_init();
+	bootblock_cpu_early_init();
+	*/
+	if (IS_ENABLED(CONFIG_UART_DEBUG))
+		pch_uart_init();
+}
+
+void bootblock_soc_init(void)
+{
+	/* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
+	if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
+		bootblock_fsp_temp_ram_init();
+
+	/*
+	 * Perform early chipset initialization before fsp memory init
+	 * example: pirq->irq programming, enabling smbus, set pmcbase
+	 * and abase, i2c programming and print platform info
+	 */
+	/* TODO: Add PCH and CPU driver
+	report_platform_info();
+	bootblock_cpu_init();
+	bootblock_pch_init();
+	*/
+}
diff --git a/src/soc/intel/common/basecode/include/bootblock.h b/src/soc/intel/common/basecode/include/bootblock.h
new file mode 100644
index 0000000..a59b5bf
--- /dev/null
+++ b/src/soc/intel/common/basecode/include/bootblock.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_BASECODE_BOOTBLOCK_H_
+#define _SOC_BASECODE_BOOTBLOCK_H_
+
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+#include <fsp/bootblock.h>
+#else
+static inline void bootblock_fsp_temp_ram_init(void) {}
+#endif
+
+#include <intelblocks/systemagent.h>
+
+/* Bootblock pre console init programing */
+void bootblock_cpu_early_init(void);
+void bootblock_pch_early_init(void);
+void pch_uart_init(void);
+
+/* Bootblock post console init programing */
+void enable_smbus(void);
+void pch_early_iorange_init(void);
+void report_platform_info(void);
+void report_memory_config(void);
+void bootblock_cpu_init(void);
+void bootblock_pch_init(void);
+
+#endif