[coreboot-gerrit] Patch set updated for coreboot: soc/intel/common/block: Add Intel XHCI driver support

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18221

-gerrit

commit 9dd393208fe8395a2803feefc935d6e505d98735
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Thu Feb 16 16:08:49 2017 +0530

    soc/intel/common/block: Add Intel XHCI driver support
    
    Create sample model for common Intel XHCI driver.
    
    Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/soc/intel/common/Makefile.inc                  |  2 +
 .../intel/common/block/include/intelblocks/xhci.h  | 22 +++++++++++
 src/soc/intel/common/block/xhci/Kconfig            |  4 ++
 src/soc/intel/common/block/xhci/Makefile.inc       |  5 +++
 src/soc/intel/common/block/xhci/xhci.c             | 44 ++++++++++++++++++++++
 5 files changed, 77 insertions(+)

diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index cf11ec2..675b9b5 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -36,6 +36,8 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c
 
 smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c
 
+CPPFLAGS_common += -I$(src)/soc/intel/common/block/include
+
 # Create and add the MRC cache to the cbfs image
 ifneq ($(CONFIG_CHROMEOS),y)
 $(obj)/mrc.cache: $(obj)/config.h
diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h
new file mode 100644
index 0000000..9ea2312
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/xhci.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_XHCI_H
+#define SOC_INTEL_XHCI_H
+
+void xhci_init(struct device *dev);
+
+#endif	/* SOC_INTEL_XHCI_H */
+
diff --git a/src/soc/intel/common/block/xhci/Kconfig b/src/soc/intel/common/block/xhci/Kconfig
new file mode 100644
index 0000000..23313d7
--- /dev/null
+++ b/src/soc/intel/common/block/xhci/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_XHCI
+	bool
+	help
+	  Intel Processor common XHCI support
diff --git a/src/soc/intel/common/block/xhci/Makefile.inc b/src/soc/intel/common/block/xhci/Makefile.inc
new file mode 100644
index 0000000..6fec7b9
--- /dev/null
+++ b/src/soc/intel/common/block/xhci/Makefile.inc
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_SOC_INTEL_COMMON_XHCI),y)
+
+ramstage-y += xhci.c
+
+endif
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
new file mode 100644
index 0000000..d45b601
--- /dev/null
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <intelblocks/xhci.h>
+
+__attribute__((weak)) void xhci_init(struct device *dev) { /* no-op */ }
+
+static struct device_operations usb_xhci_ops = {
+	.read_resources		= &pci_dev_read_resources,
+	.set_resources		= &pci_dev_set_resources,
+	.enable_resources	= &pci_dev_enable_resources,
+	.init			= xhci_init,
+};
+
+static const unsigned short pci_device_ids[] = {
+	0x5aa8, /* ApolloLake */
+	0x31a8, /* GLK */
+	0x9d2f, /* SunRisePoint LP */
+	0xa12f, /* KBL-H*/
+	0
+};
+
+static const struct pci_driver pch_usb_xhci __pci_driver = {
+	.ops	 = &usb_xhci_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices	 = pci_device_ids,
+};