[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: Add config for enable/disable voltage margining

[Rizwan Qureshi (rizwan.qureshi@intel.com)]

Rizwan Qureshi (rizwan.qureshi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18469

-gerrit

commit 147c5d2cffd099f988d25465775cabc24f63f3ed
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Thu Feb 23 14:43:39 2017 +0530

    soc/intel/skylake: Add config for enable/disable voltage margining
    
    Voltage margining should be disabled for S0ix to work, FSP
    provides a UPD to enable/disable the voltage margining when
    SLP_S0# is asserted, expose the same as a config option
    in devicetree.cb.
    
    Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
 src/soc/intel/skylake/chip.h       | 8 ++++++++
 src/soc/intel/skylake/chip_fsp20.c | 1 +
 2 files changed, 9 insertions(+)

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 07cb8b1..f122a4c 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -332,6 +332,14 @@ struct soc_intel_skylake_config {
 	 * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s
 	 */
 	u8 PmConfigPwrBtnOverridePeriod;
+
+	/*
+	 * PCH Pm Slp S0 Voltage Margining Enable
+	 * Indicates platform has support for VCCPrim_Core Voltage Margining
+	 * in SLP_S0# asserted state.
+	 */
+	u8 PchPmSlpS0VmEnable;
+
 	/*
 	 * Reset Power Cycle Duration could be customized in the unit of second.
 	 * PCH HW default is 4 seconds, and range is 1~4 seconds.
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 2b50d0c..9042451 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -220,6 +220,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchPmPwrBtnOverridePeriod =
 				config->PmConfigPwrBtnOverridePeriod;
 	params->PchPmPwrCycDur = config->PmConfigPwrCycDur;
+	params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable;
 	params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
 	params->PchSirqMode = config->SerialIrqConfigSirqMode;