[coreboot-gerrit] New patch to review for coreboot: mainboard/google/eve: enable SGX [For testing]
Robbie Zhang (robbie.zhang@intel.com)
gerrit at coreboot.org
Tue Feb 21 23:09:43 CET 2017
Robbie Zhang (robbie.zhang at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18446
-gerrit
commit a3c8d808f124c19824243bad6f39bced70b10126
Author: Robbie Zhang <robbie.zhang at intel.com>
Date: Tue Feb 21 14:07:15 2017 -0800
mainboard/google/eve: enable SGX [For testing]
prmrr_size is set to 32MiB.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified SGX is activated successfully, and boot.
Change-Id: I830dd954406ddf3e298f4f10572b6f281280503a
Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
---
src/mainboard/google/eve/devicetree.cb | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index e40f0a3..3b72ff8 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -194,6 +194,8 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
register "tdp_pl2_override" = "7"
register "tcc_offset" = "10"
+ register "PrmrrSize" = "0x02000000"
+ register "sgx_enable" = "1"
device cpu_cluster 0 on
device lapic 0 on end
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