[coreboot-gerrit] New patch to review for coreboot: amd/pi/hudson: Add SPI definitions to header

[Marc Jones (marc@marcjonesconsulting.com)]

Marc Jones (marc at marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18441

-gerrit

commit 79405e1a945132194776b9245bffea040c11caec
Author: Marshall Dawson <marshalldawson3rd at gmail.com>
Date:   Sun Jan 29 17:29:46 2017 -0700

    amd/pi/hudson: Add SPI definitions to header
    
    Add defines that will be used later for setting the fastest settings
    in the SPI controller.
    
    Original-Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
    Original-Reviewed-by: Marc Jones <marcj303 at gmail.com>
    (cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c)
    
    Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/southbridge/amd/pi/hudson/hudson.h | 38 ++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 7835f68..73dd0e9 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -120,6 +120,44 @@
 #define DECODE_ENABLE_ACPIUC_PORT     (BIT30)
 #define DECODE_ENABLE_ADLIB_PORT      (BIT31)
 
+#define SPI_CNTRL0                    ((void *)(SPI_BASE_ADDRESS + 0x00))
+#define SPI_READ_MODE_MASK            (BIT30 | BIT29 | BIT18)
+/* Nominal is 16.7MHz on older devices, 33MHz on newer */
+#define SPI_READ_MODE_NOM             0x00000000
+#define SPI_READ_MODE_DUAL112         (        BIT29        )
+#define SPI_READ_MODE_QUAD114         (        BIT29 | BIT18)
+#define SPI_READ_MODE_DUAL122         (BIT30                )
+#define SPI_READ_MODE_QUAD144         (BIT30 |         BIT18)
+#define SPI_READ_MODE_NORMAL66        (BIT30 | BIT29        )
+/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */
+#define SPI_READ_MODE_FAST_HUDSON1    (                BIT18)
+#define SPI_READ_MODE_FAST            (BIT30 | BIT29 | BIT18)
+#define SPI_ARB_ENABLE                BIT19
+
+#define SPI_CNTRL1                    ((void *)(SPI_BASE_ADDRESS + 0x0c))
+/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */
+#define SPI_CNTRL1_SPEED_MASK         (BIT15 | BIT14 | BIT13 | BIT12)
+#define SPI_NORM_SPEED_SH             12
+#define SPI_FAST_SPEED_SH             8
+
+#define SPI100_ENABLE                 ((void *)(SPI_BASE_ADDRESS + 0x20))
+#define SPI_USE_SPI100                (BIT0)
+
+#define SPI100_SPEED_CONFIG           ((void *)(SPI_BASE_ADDRESS + 0x22))
+#define SPI_SPEED_66M                 (0x0)
+#define SPI_SPEED_33M                 (             BIT0)
+#define SPI_SPEED_22M                 (      BIT1       )
+#define SPI_SPEED_16M                 (      BIT1 | BIT0)
+#define SPI_SPEED_100M                (BIT2             )
+#define SPI_SPEED_800K                (BIT2 |       BIT0)
+#define SPI_NORM_SPEED_NEW_SH         12
+#define SPI_FAST_SPEED_NEW_SH         8
+#define SPI_ALT_SPEED_NEW_SH          4
+#define SPI_TPM_SPEED_NEW_SH          0
+
+#define SPI100_HOST_PREF_CONFIG       ((void *)(SPI_BASE_ADDRESS + 0x2c))
+#define SPI_RD4DW_EN_HOST             BIT15
+
 static inline int hudson_sata_enable(void)
 {
 	/* True if IDE or AHCI. */