[coreboot-gerrit] New patch to review for coreboot: amd/pi: Add verstage support
Marc Jones (marc@marcjonesconsulting.com)
gerrit at coreboot.org
Tue Feb 21 21:36:59 CET 2017
Marc Jones (marc at marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18439
-gerrit
commit 9bb7b9928727e79e5a5671f8230cde9744dd545c
Author: Marshall Dawson <marshalldawson3rd at gmail.com>
Date: Thu Feb 9 16:19:34 2017 -0700
amd/pi: Add verstage support
This patch takes hints from the work in commits 75c51d9 and 909c512.
Give PI-based systems the capability of running a SEPARATE_VERSTAGE.
This adds
* A verstage.c file to that initiates loading romstage (and verification)
* A new entry point in car.c that will be used when there is a separate
verstage
* Makefile flags and verstage-y additions for cpu and southbridge
* Besides AMD binary-PI changes, the x86 lapic timer is also now
included into verstage
This has been tested on Stoney (00670F000) and Gardenia. Although
additional APUs' makefiles are modified, none of those platforms are
assumed to support verstage at this time.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
Original-Reviewed-by: Marc Jones <marcj303 at gmail.com>
(cherry picked from commit 15ce30cbd9d20aa0f5a5516e5f3bee7eab069852)
Change-Id: Ie43d87908c2d83b42b95b306419156e85993f7bd
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
src/cpu/amd/pi/00630F01/Makefile.inc | 1 +
src/cpu/amd/pi/00660F01/Makefile.inc | 1 +
src/cpu/amd/pi/00670F00/Makefile.inc | 1 +
src/cpu/amd/pi/00730F01/Makefile.inc | 1 +
src/cpu/amd/pi/Makefile.inc | 4 ++++
src/cpu/amd/pi/car.c | 6 ++++++
src/cpu/amd/pi/car.h | 3 +++
src/cpu/amd/pi/romstage_after_verstage.S | 23 +++++++++++++++++++++++
src/cpu/amd/pi/verstage.c | 23 +++++++++++++++++++++++
src/cpu/x86/lapic/Makefile.inc | 1 +
src/southbridge/amd/pi/hudson/Makefile.inc | 3 +++
src/vendorcode/amd/pi/Makefile.inc | 2 ++
12 files changed, 69 insertions(+)
diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc
index 98a7050..9dce0a8 100644
--- a/src/cpu/amd/pi/00630F01/Makefile.inc
+++ b/src/cpu/amd/pi/00630F01/Makefile.inc
@@ -13,6 +13,7 @@
# GNU General Public License for more details.
#
+verstage-y += fixme.c
romstage-y += fixme.c
ramstage-y += fixme.c
diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc
index 6c6a2b8..acaf1f4 100644
--- a/src/cpu/amd/pi/00660F01/Makefile.inc
+++ b/src/cpu/amd/pi/00660F01/Makefile.inc
@@ -13,6 +13,7 @@
# GNU General Public License for more details.
#
+verstage-y += fixme.c
romstage-y += fixme.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/pi/00670F00/Makefile.inc b/src/cpu/amd/pi/00670F00/Makefile.inc
index 6c6a2b8..acaf1f4 100644
--- a/src/cpu/amd/pi/00670F00/Makefile.inc
+++ b/src/cpu/amd/pi/00670F00/Makefile.inc
@@ -13,6 +13,7 @@
# GNU General Public License for more details.
#
+verstage-y += fixme.c
romstage-y += fixme.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc
index 9367b45..57cabb3 100644
--- a/src/cpu/amd/pi/00730F01/Makefile.inc
+++ b/src/cpu/amd/pi/00730F01/Makefile.inc
@@ -13,6 +13,7 @@
# GNU General Public License for more details.
#
+verstage-y += fixme.c
romstage-y += fixme.c
ramstage-y += fixme.c
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index ce60833..972c11d 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -18,7 +18,11 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
+verstage-y += verstage.c
+verstage-y += car.c
+
romstage-y += car.c
+romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
romstage-y += s3_resume.c
ramstage-y += s3_resume.c
diff --git a/src/cpu/amd/pi/car.c b/src/cpu/amd/pi/car.c
index 62c5338..f66f94f 100644
--- a/src/cpu/amd/pi/car.c
+++ b/src/cpu/amd/pi/car.c
@@ -66,6 +66,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cache_as_ram_stage_main();
}
+void romstage_after_verstage(void)
+{
+ /* This does not return. */
+ cache_as_ram_stage_main();
+}
+
unsigned long __attribute__((weak)) car_bist_mask_bist(unsigned long bist)
{
return bist;
diff --git a/src/cpu/amd/pi/car.h b/src/cpu/amd/pi/car.h
index 98da75d..fdf1420 100644
--- a/src/cpu/amd/pi/car.h
+++ b/src/cpu/amd/pi/car.h
@@ -17,6 +17,9 @@
#ifndef PI_SPLIT_CAR_H
#define PI_SPLIT_CAR_H
+/* Entry points from the cache-as-ram assembly code */
+void romstage_after_verstage(void);
+
/* Early initialization immediately after CAR setup */
void cache_as_ram_stage_main(void);
diff --git a/src/cpu/amd/pi/romstage_after_verstage.S b/src/cpu/amd/pi/romstage_after_verstage.S
new file mode 100644
index 0000000..ce17ebd
--- /dev/null
+++ b/src/cpu/amd/pi/romstage_after_verstage.S
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "gcccar.inc"
+
+.text
+.global car_stage_entry, disable_cache_as_ram
+car_stage_entry:
+ call romstage_after_verstage
+
+ #include "after_raminit.S"
diff --git a/src/cpu/amd/pi/verstage.c b/src/cpu/amd/pi/verstage.c
new file mode 100644
index 0000000..c8551dd
--- /dev/null
+++ b/src/cpu/amd/pi/verstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/amd/pi/car.h>
+#include <program_loading.h>
+
+void cache_as_ram_stage_main(void)
+{
+ run_romstage();
+ /* Will not return to here. */
+}
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index 9df2c5f..58f67b2 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -1,6 +1,7 @@
ramstage-y += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-y += secondary.S
+verstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
bootblock-y += boot_cpu.c
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 2153c62..4bd599b 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -42,8 +42,10 @@ ramstage-y += sd.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
+verstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+verstage-y += early_setup.c
romstage-y += early_setup.c
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
romstage-y += imc.c
@@ -51,6 +53,7 @@ ramstage-y += imc.c
endif
ifeq ($(CONFIG_HUDSON_UART), y)
+verstage-y += uart.c
romstage-y += uart.c
ramstage-y += uart.c
endif
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 2cd18c1..b782540 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -77,6 +77,7 @@ export AGESA_INC := $(AGESA_INC)
export AGESA_CFLAGS := $(AGESA_CFLAGS)
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
+CC_verstage := $(CC_verstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
@@ -139,6 +140,7 @@ $(obj)/agesa/libagesa.a: $(call src-to-obj,libagesa,$(agesa_src_files))
@printf " AGESA $(subst $(obj)/,,$(@))\n"
ar rcs $@ $+
+verstage-libs += $(obj)/agesa/libagesa.a
romstage-libs += $(obj)/agesa/libagesa.a
ramstage-libs += $(obj)/agesa/libagesa.a
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