[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Expand USB OC pins definition to support PCH-H

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f296ce91b90ba845b1ff5ca35e98e52e884694cf
Author: Teo Boon Tiong <boon.tiong.teo at intel.com>
Date:   Tue Feb 14 22:16:58 2017 +0800

    soc/intel/skylake: Expand USB OC pins definition to support PCH-H
    
    Currently the USB OC pins definition only being defined up to OC3.
    For PCH-H, OC4 and OC5 are needed, so add both into OC pin enum.
    
    Changes is being verified and booted to Yocto with Saddle Brook.
    
    Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb
    Signed-off-by: Teo Boon Tiong <boon.tiong.teo at intel.com>
    Reviewed-on: https://review.coreboot.org/18364
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/18364 for details.

-gerrit