[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: Disable s0ix if not enabled in devicetree

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18394

-gerrit

commit 6dce486e00169e43720cd1dc0613a2a03489dff3
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Feb 17 17:16:43 2017 -0800

    soc/intel/skylake: Disable s0ix if not enabled in devicetree
    
    There is an enable_s0ix config option in the devicetree that should
    be used to disable it when not set:
    
    - do not export C8/C9/C10 C-states in _CST
    - do not enable SLP_S0 in FSP
    
    BUG=chrome-os-partner:58666
    TEST=test on eve board to ensure that OS only sees 3 ACPI C-states
    instead of 6 and that it no longer attempts to enter C10
    
    Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/acpi.c       | 3 ---
 src/soc/intel/skylake/chip_fsp20.c | 1 +
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 2f8cf51..4f2dafd 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -146,9 +146,6 @@ static int cstate_set_non_s0ix[] = {
 	C_STATE_C1E,
 	C_STATE_C3,
 	C_STATE_C7S_LONG_LAT,
-	C_STATE_C8,
-	C_STATE_C9,
-	C_STATE_C10
 };
 
 static int get_cores_per_package(void)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 9c87b65..97a37e8 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -205,6 +205,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride;
 	params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
 	params->PchPmDeepSxPol = config->PmConfigDeepSxPol;
+	params->PchPmSlpS0Enable = config->s0ix_enable;
 	params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert;
 	params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
 	params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert;