[coreboot-gerrit] Patch set updated for coreboot: lynxpoint/broadwell: fix PCH power optimizer

[Matt DeVillier (matt.devillier@gmail.com)]

Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18385

-gerrit

commit c3622a5f162e37a532b02eac2aec809920627be8
Author: Matt DeVillier <matt.devillier at gmail.com>
Date:   Thu Feb 16 11:36:16 2017 -0600

    lynxpoint/broadwell: fix PCH power optimizer
    
    Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
    Configuration; offset 0x33c8) causes pre-OS display init to fail
    on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
    driver is run after the register is set. A re-examination of
    Intel's reference code reveals that bit 7 should be set for the
    LP PCH, and bit 27 for non-LP, but not both simultaneously.
    
    The previous workaround was to disable the entire power optimizer
    section via a Kconfig option, which isn't ideal.
    
    Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
    observe functional pre-OS video output
    
    Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
    Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
 src/soc/intel/broadwell/lpc.c         | 2 +-
 src/southbridge/intel/lynxpoint/lpc.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index c1600c5..610b977 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -262,7 +262,7 @@ static const struct reg_script pch_pm_init_script[] = {
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
 	/* Power Optimizer */
 	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
-	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
+	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00000080),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616),
 	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005),
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 04cb0bd..d295c88 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -347,7 +347,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
 	RCBA_RMW_REG_32(0x3350,  0, 0x022ddfff),
 	RCBA_RMW_REG_32(0x3354,  0, 0x00000001),
 	RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000),  /* Power Optimizer */
-	RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080),  /* Power Optimizer */
+	RCBA_RMW_REG_32(0x33c8, ~0, 0x00000080),  /* Power Optimizer */
 	RCBA_RMW_REG_32(0x2b10,  0, 0x0000883c),  /* Power Optimizer */
 	RCBA_RMW_REG_32(0x2b14,  0, 0x1e0a4616),  /* Power Optimizer */
 	RCBA_RMW_REG_32(0x2b24,  0, 0x40000005),  /* Power Optimizer */