[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Expand USB OC pins definition to support PCH-H

[Boon Tiong Teo (boon.tiong.teo@intel.com)]

Boon Tiong Teo (boon.tiong.teo at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18364

-gerrit

commit 93986660e2da1b22c25e0f182fd921050ce887bc
Author: Teo Boon Tiong <boon.tiong.teo at intel.com>
Date:   Tue Feb 14 22:16:58 2017 +0800

    soc/intel/skylake: Expand USB OC pins definition to support PCH-H
    
    Currently the USB OC pins definition only being defined up to OC3.
    For PCH-H, OC4 and OC5 are needed, without these, it will causes
    build fail for Rvp11 or Saddle Brook platform.
    
    Changes is being verified and booted to Yocto with Saddle Brook.
    
    Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb
    Signed-off-by: Teo Boon Tiong <boon.tiong.teo at intel.com>
---
 src/soc/intel/skylake/include/soc/usb.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h
index 77a94a8..d4f7cc5 100644
--- a/src/soc/intel/skylake/include/soc/usb.h
+++ b/src/soc/intel/skylake/include/soc/usb.h
@@ -51,6 +51,8 @@ enum {
 	OC1,
 	OC2,
 	OC3,
+	OC4,
+	OC5,
 	OC_SKIP = 8, /* Skip OC programming */
 };