[coreboot-gerrit] New patch to review for coreboot: southbridge/intel/bd82x6x: Use correct EHCI address for USBDEBUG
Tobias Diedrich (ranma+coreboot@tdiedrich.de)
gerrit at coreboot.org
Sun Feb 12 23:04:10 CET 2017
Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18353
-gerrit
commit be651ab1f5db2d21dafc11cae83568a11056ec0e
Author: Tobias Diedrich <ranma+openocd at tdiedrich.de>
Date: Sun Feb 12 22:58:37 2017 +0100
southbridge/intel/bd82x6x: Use correct EHCI address for USBDEBUG
The bd82x6x hardcoded EHCI bar adresses (0xe8000[04]00) don't match the
CONFIG_EHCI_BAR default of 0xfef00000.
This copies the defines from southbridge/intel/lynxpoint/early_usb.c
so that the early EHCI bar setup is using CONFIG_EHCI_BAR and
CONFIG_USBDEBUG_HCD_INDEX to determine the correct bar addresses.
Change-Id: I6ee6089c9e5f3bc5f457eae47c18c2473fa42571
Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
src/southbridge/intel/bd82x6x/early_usb_mrc.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
index 8fac3c7..5c2b696 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
@@ -20,8 +20,16 @@
#include <device/pci_def.h>
#include "pch.h"
-#define PCH_EHCI1_TEMP_BAR0 0xe8000000
-#define PCH_EHCI2_TEMP_BAR0 0xe8000400
+/* HCD_INDEX==2 selects 0:1a.0 (PCH_EHCI2), any other index
+ * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
+ */
+#if CONFIG_USBDEBUG_HCD_INDEX != 2
+#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
+#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
+#else
+#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
+#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
+#endif
/*
* Setup USB controller MMIO BAR to prevent the
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