[coreboot-gerrit] New patch to review for coreboot: lynxpoint bd82x6x: Enable PCI-to-PCI bridge

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18330

-gerrit

commit d3d763f15ce8caa3d72d7bba61c6419a3b671680
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Feb 11 17:31:25 2017 +0200

    lynxpoint bd82x6x: Enable PCI-to-PCI bridge
    
    Once the PCI command register is written the bridge forwards
    future IO and memory regions, as programmed in the respective base
    and limit registers, to the secondary PCI bus.
    
    It was previously argumented this is copy-paste and never known
    to be required for these more recent platforms:
       https://review.coreboot.org/#/c/2706/
    
    Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/southbridge/intel/bd82x6x/pci.c   | 9 ---------
 src/southbridge/intel/lynxpoint/pci.c | 5 -----
 2 files changed, 14 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index 68c4bb2..85e431e 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -59,7 +59,6 @@ static void pci_init(struct device *dev)
 	pci_write_config16(dev, SECSTS, reg16);
 }
 
-#undef PCI_BRIDGE_UPDATE_COMMAND
 static void ich_pci_dev_enable_resources(struct device *dev)
 {
 	const struct pci_operations *ops;
@@ -79,16 +78,8 @@ static void ich_pci_dev_enable_resources(struct device *dev)
 
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;
-#ifdef PCI_BRIDGE_UPDATE_COMMAND
-	/* If we write to PCI_COMMAND, on some systems
-	 * this will cause the ROM and APICs not being visible
-	 * anymore.
-	 */
 	printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
 	pci_write_config16(dev, PCI_COMMAND, command);
-#else
-	printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
-#endif
 }
 
 static void ich_pci_bus_enable_resources(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c
index 68c4bb2..e2e052b 100644
--- a/src/southbridge/intel/lynxpoint/pci.c
+++ b/src/southbridge/intel/lynxpoint/pci.c
@@ -59,7 +59,6 @@ static void pci_init(struct device *dev)
 	pci_write_config16(dev, SECSTS, reg16);
 }
 
-#undef PCI_BRIDGE_UPDATE_COMMAND
 static void ich_pci_dev_enable_resources(struct device *dev)
 {
 	const struct pci_operations *ops;
@@ -79,16 +78,12 @@ static void ich_pci_dev_enable_resources(struct device *dev)
 
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;
-#ifdef PCI_BRIDGE_UPDATE_COMMAND
 	/* If we write to PCI_COMMAND, on some systems
 	 * this will cause the ROM and APICs not being visible
 	 * anymore.
 	 */
 	printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
 	pci_write_config16(dev, PCI_COMMAND, command);
-#else
-	printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
-#endif
 }
 
 static void ich_pci_bus_enable_resources(struct device *dev)