[coreboot-gerrit] Patch set updated for coreboot: ddr3 spd: move accessor code into lib/spd_bin.c
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Feb 10 16:52:53 CET 2017
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18265
-gerrit
commit 47fb4edfddc1061ddc6cd6a0ab40dcabcb8edbf8
Author: Patrick Georgi <pgeorgi at chromium.org>
Date: Sat Jan 28 15:59:25 2017 +0100
ddr3 spd: move accessor code into lib/spd_bin.c
It's an attempt to consolidate the access code, even if there are still
multiple implementations in the code.
Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
src/device/Kconfig | 4 --
src/device/dram/Makefile.inc | 2 +-
src/device/dram/spd_cache.c | 67 -----------------------------
src/include/spd_bin.h | 3 ++
src/include/spd_cache.h | 26 -----------
src/lib/Makefile.inc | 4 +-
src/lib/spd_bin.c | 44 +++++++++++++++++++
src/mainboard/amd/db-ft3b-lc/Kconfig | 1 -
src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 2 +-
src/mainboard/bap/ode_e20XX/Kconfig | 1 -
src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 2 +-
src/mainboard/bap/ode_e21XX/Kconfig | 1 -
src/mainboard/gizmosphere/gizmo/Kconfig | 1 -
src/mainboard/gizmosphere/gizmo2/Kconfig | 1 -
src/mainboard/pcengines/apu1/BiosCallOuts.c | 2 +-
src/mainboard/pcengines/apu1/Kconfig | 1 -
src/mainboard/pcengines/apu2/BiosCallOuts.c | 2 +-
src/mainboard/pcengines/apu2/Kconfig | 1 -
src/northbridge/amd/agesa/def_callouts.c | 2 +-
src/northbridge/amd/pi/def_callouts.c | 2 +-
20 files changed, 56 insertions(+), 113 deletions(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index d1f5694..4036a3d 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -210,10 +210,6 @@ config SMBUS_HAS_AUX_CHANNELS
bool
default n
-config SPD_CACHE
- bool
- default n
-
config PCI
bool
default n
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
index 05f440b..b1a6755 100644
--- a/src/device/dram/Makefile.inc
+++ b/src/device/dram/Makefile.inc
@@ -1 +1 @@
-romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c
+romstage-y += ddr3.c
diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c
deleted file mode 100644
index a74e4a7..0000000
--- a/src/device/dram/spd_cache.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <device/dram/ddr3.h>
-#include <spd_cache.h>
-#include <stdint.h>
-#include <string.h>
-
-#define SPD_SIZE 128
-
-_Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ");
-
-int read_ddr3_spd_from_cbfs(u8 *buf, int idx)
-{
- const int SPD_CRC_HI = 127;
- const int SPD_CRC_LO = 126;
-
- const char *spd_file;
- size_t spd_file_len = 0;
- size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE;
-
- spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
- &spd_file_len);
- if (!spd_file)
- printk(BIOS_EMERG, "file [spd.bin] not found in CBFS");
- if (spd_file_len < min_len)
- printk(BIOS_EMERG, "Missing SPD data.");
- if (!spd_file || spd_file_len < min_len)
- return -1;
-
- memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE);
-
- u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE);
-
- if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
- || (buf[SPD_CRC_LO] != (crc & 0xff))
- || (buf[SPD_CRC_HI] != (crc >> 8))) {
- printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n",
- buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc);
- buf[SPD_CRC_LO] = crc & 0xff;
- buf[SPD_CRC_HI] = crc >> 8;
- u16 i;
- printk(BIOS_WARNING, "\nDisplay the SPD");
- for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) {
- if((i % 16) == 0x00)
- printk(BIOS_WARNING, "\n%02x: ", i);
- printk(BIOS_WARNING, "%02x ", buf[i]);
- }
- printk(BIOS_WARNING, "\n");
- }
- return 0;
-}
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
index a0c1bbd..4d5ce2f 100644
--- a/src/include/spd_bin.h
+++ b/src/include/spd_bin.h
@@ -54,4 +54,7 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index);
void dump_spd_info(struct spd_block *blk);
void get_spd_smbus(struct spd_block *blk);
+/* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and
+ verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */
+int read_ddr3_spd_from_cbfs(u8 *buf, int idx);
#endif
diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h
deleted file mode 100644
index 912aa64..0000000
--- a/src/include/spd_cache.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SPD_CACHE_H_
-#define _SPD_CACHE_H_
-
-#include <stdint.h>
-
-#if IS_ENABLED(CONFIG_SPD_CACHE)
-int read_ddr3_spd_from_cbfs(u8 *buf, int idx);
-#else
-static inline int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { return -1; }
-#endif
-
-#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 38b3c12..977770f 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -287,9 +287,9 @@ ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb
endif # CONFIG_RAMSTAGE_LIBHWBASE
-ifeq ($(CONFIG_GENERIC_SPD_BIN),y)
-romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c
+romstage-y += spd_bin.c
+ifeq ($(CONFIG_GENERIC_SPD_BIN),y)
LIB_SPD_BIN = $(obj)/spd.bin
LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index 4108839..8f358bb 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -19,6 +19,7 @@
#include <spd_bin.h>
#include <string.h>
#include <device/early_smbus.h>
+#include <device/dram/ddr3.h>
static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL;
@@ -164,3 +165,46 @@ void get_spd_smbus(struct spd_block *blk)
update_spd_len(blk);
}
+
+#if CONFIG_DIMM_SPD_SIZE == 128
+int read_ddr3_spd_from_cbfs(u8 *buf, int idx)
+{
+ const int SPD_CRC_HI = 127;
+ const int SPD_CRC_LO = 126;
+
+ const char *spd_file;
+ size_t spd_file_len = 0;
+ size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE;
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+ if (!spd_file)
+ printk(BIOS_EMERG, "file [spd.bin] not found in CBFS");
+ if (spd_file_len < min_len)
+ printk(BIOS_EMERG, "Missing SPD data.");
+ if (!spd_file || spd_file_len < min_len)
+ return -1;
+
+ memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE);
+
+ u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE);
+
+ if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
+ || (buf[SPD_CRC_LO] != (crc & 0xff))
+ || (buf[SPD_CRC_HI] != (crc >> 8))) {
+ printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n",
+ buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc);
+ buf[SPD_CRC_LO] = crc & 0xff;
+ buf[SPD_CRC_HI] = crc >> 8;
+ u16 i;
+ printk(BIOS_WARNING, "\nDisplay the SPD");
+ for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) {
+ if((i % 16) == 0x00)
+ printk(BIOS_WARNING, "\n%02x: ", i);
+ printk(BIOS_WARNING, "%02x ", buf[i]);
+ }
+ printk(BIOS_WARNING, "\n");
+ }
+ return 0;
+}
+#endif
diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig
index 7bf3c86..3999039 100644
--- a/src/mainboard/amd/db-ft3b-lc/Kconfig
+++ b/src/mainboard/amd/db-ft3b-lc/Kconfig
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
- select SPD_CACHE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
index 2ceb5c8..e6773b8 100644
--- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
@@ -24,7 +24,7 @@
#include "imc.h"
#endif
#include <stdlib.h>
-#include <spd_cache.h>
+#include <spd_bin.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig
index ee26772..6631ac8 100644
--- a/src/mainboard/bap/ode_e20XX/Kconfig
+++ b/src/mainboard/bap/ode_e20XX/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_4096
select GFXUMA
select SUPERIO_FINTEK_F81866D
- select SPD_CACHE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
index 10ec422..9b241fc 100644
--- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
@@ -25,7 +25,7 @@
#endif
#include "hudson.h"
#include <stdlib.h>
-#include <spd_cache.h>
+#include <spd_bin.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig
index 60a59ac..c8472c4 100644
--- a/src/mainboard/bap/ode_e21XX/Kconfig
+++ b/src/mainboard/bap/ode_e21XX/Kconfig
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_8192
select GFXUMA
select SUPERIO_FINTEK_F81866D
- select SPD_CACHE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig
index 8109019..4177b1d 100644
--- a/src/mainboard/gizmosphere/gizmo/Kconfig
+++ b/src/mainboard/gizmosphere/gizmo/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA
- select SPD_CACHE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig
index 349f827..f5509f6 100644
--- a/src/mainboard/gizmosphere/gizmo2/Kconfig
+++ b/src/mainboard/gizmosphere/gizmo2/Kconfig
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
- select SPD_CACHE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c
index f35cbd2..7604277 100644
--- a/src/mainboard/pcengines/apu1/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c
@@ -15,7 +15,7 @@
#include "AGESA.h"
#include "amdlib.h"
-#include <spd_cache.h>
+#include <spd_bin.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "heapManager.h"
#include "SB800.h"
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index f882b78..5e927cc 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select BOARD_ROMSIZE_KB_2048
- select SPD_CACHE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index 221b315..ab9d521 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -15,7 +15,7 @@
#include "AGESA.h"
#include "amdlib.h"
-#include <spd_cache.h>
+#include <spd_bin.h>
#include <northbridge/amd/pi/BiosCallOuts.h>
#include "Ids.h"
#include "OptionsIds.h"
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index de42721..4303b84 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
- select SPD_CACHE
select HUDSON_DISABLE_IMC
select USE_BLOBS
diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c
index 953774a..0805c02 100644
--- a/src/northbridge/amd/agesa/def_callouts.c
+++ b/src/northbridge/amd/agesa/def_callouts.c
@@ -15,7 +15,7 @@
*/
#include <cbfs.h>
-#include <spd_cache.h>
+#include <spd_bin.h>
#include "AGESA.h"
#include "amdlib.h"
diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c
index e38d807..6b8aaee 100644
--- a/src/northbridge/amd/pi/def_callouts.c
+++ b/src/northbridge/amd/pi/def_callouts.c
@@ -15,7 +15,7 @@
*/
#include <cbfs.h>
-#include <spd_cache.h>
+#include <spd_bin.h>
#include "AGESA.h"
#include "amdlib.h"
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