[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18288

-gerrit

commit 8295c60a15eb88b50035e243d6e072c8c66fc942
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Fri Feb 3 19:05:27 2017 +0530

    soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs
    
    This patch enables ACPI timer emulation on all the logical cpus.
    
    BUG=chrome-os-partner:62438
    BRANCH=NONE
    TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init.
    
    Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/soc/intel/skylake/cpu.c             | 24 ++++++++++++++++++++----
 src/soc/intel/skylake/include/soc/msr.h |  5 +++++
 2 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 684680d..a3c4539 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -37,6 +37,7 @@
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
+#include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/smm.h>
 #include <soc/systemagent.h>
@@ -351,6 +352,20 @@ static void configure_mca(void)
 		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 }
 
+/*
+ * The emulated ACPI timer allows disabling of the ACPI timer
+ * (PM1_TMR) to have no impart on the system.
+ */
+static void configure_emulation_timer(void)
+{
+	msr_t msr;
+
+	msr.hi = uCODE_TMR_EMULATION;
+	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
+			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
+	wrmsr(MSR_EMULATE_PM_TIMER, msr);
+}
+
 /* All CPUs including BSP will run the following function. */
 static void cpu_core_init(device_t cpu)
 {
@@ -367,6 +382,9 @@ static void cpu_core_init(device_t cpu)
 	/* Configure Intel Speed Shift */
 	configure_isst();
 
+	/* Enable ACPI Timer Emulation via MSR 0x121 */
+	configure_emulation_timer();
+
 	/* Enable Direct Cache Access */
 	configure_dca_cap();
 
@@ -506,8 +524,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 	return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1);
 }
 
-/*
- * Do CPU MP Init before FSP Silicon Init
- */
+/* Do CPU MP Init before FSP Silicon Init */
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL);
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL);
\ No newline at end of file
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL);
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 4d295e1..405b13f 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -26,6 +26,11 @@
 #define  PLATFORM_INFO_SET_TDP		(1 << 29)
 #define MSR_PMG_CST_CONFIG_CONTROL	0xe2
 #define MSR_PMG_IO_CAPTURE_BASE		0xe4
+#define MSR_EMULATE_PM_TIMER		0x121
+#define  EMULATE_PM_TMR_EN		(1 << 16)
+#define  uCODE_TMR_EMULATION	        0x262E8B51
+#define  EMULATE_DELAY_OFFSET_VALUE	20
+#define  EMULATE_DELAY_VALUE		0x13
 #define MSR_FEATURE_CONFIG		0x13c
 #define SMM_MCA_CAP_MSR			0x17d
 #define  SMM_CPU_SVRSTR_BIT		57