[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake:[WIP] Add option to disable host reads to PMC XRAM

[Rizwan Qureshi (rizwan.qureshi@intel.com)]

Rizwan Qureshi (rizwan.qureshi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18319

-gerrit

commit fdf5429fadb1d975b729d468a9aa4f82f25d34db
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Fri Feb 10 15:58:24 2017 +0530

    soc/intel/skylake:[WIP] Add option to disable host reads to PMC XRAM
    
    FSP exposes a UPD to enable/disable host reads to PMC XRAM,
    mirror the same in skylake static.c to make it configurable
    from devicetree.
    
    Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
 src/mainboard/google/poppy/devicetree.cb | 3 +++
 src/soc/intel/skylake/chip.h             | 3 +++
 src/soc/intel/skylake/chip_fsp20.c       | 2 +-
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb
index 38d58c7..f4e4fe3 100644
--- a/src/mainboard/google/poppy/devicetree.cb
+++ b/src/mainboard/google/poppy/devicetree.cb
@@ -52,6 +52,9 @@ chip soc/intel/skylake
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
 	register "PmTimerDisabled" = "1"
 	register "SendVrMbxCmd" = "1"                  # IMVP8 workaround
+	#When set to true, this disallows host reads to PMC XRAM
+	register "PchPmPmcReadDisable" = "0"
+
 
 	register "pirqa_routing" = "PCH_IRQ11"
 	register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 1b69952..c69133b 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -376,6 +376,9 @@ struct soc_intel_skylake_config {
 	/* Enable/Disable VMX feature */
 	u8 VmxEnable;
 
+	/* When set to true, this disallows host reads to PMC XRAM */
+	u8 PchPmPmcReadDisable;
+
 	/* Statically clock gate 8254 PIT. */
 	u8 clock_gate_8254;
 
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index ebd3134..64db164 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -239,7 +239,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 * 100b - VR specific command sent for MPS VR decay issue
 	 */
 	params->SendVrMbxCmd1 = config->SendVrMbxCmd;
-
+	tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
 	soc_irq_settings(params);
 }