[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Perform CPU MP Init before FSP-S Init
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Thu Feb 9 14:41:19 CET 2017
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18287
-gerrit
commit c28200936ada5fffda807071d963338510d88457
Author: Subrata Banik <subrata.banik at intel.com>
Date: Fri Feb 3 18:57:49 2017 +0530
soc/intel/skylake: Perform CPU MP Init before FSP-S Init
As per BWG, CPU MP Init (loading ucode) should be done prior
to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry
(before FSP-S call).
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Boot to OS with all threads enabled.
Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
src/soc/intel/skylake/chip.c | 4 +--
src/soc/intel/skylake/chip_fsp20.c | 4 +--
src/soc/intel/skylake/cpu.c | 32 +++++++++++++++-------
src/soc/intel/skylake/include/fsp11/soc/ramstage.h | 3 +-
src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 3 +-
5 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index c64a8df..060c4ee 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -49,7 +49,7 @@ static struct device_operations pci_domain_ops = {
};
static struct device_operations cpu_bus_ops = {
- .init = &soc_init_cpus,
+ .init = DEVICE_NOOP,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.acpi_fill_ssdt_generator = generate_cpu_entries,
#endif
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index ebd3134..f1a32c4 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2016-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -59,7 +59,7 @@ static struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
- .init = &soc_init_cpus,
+ .init = DEVICE_NOOP,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.acpi_fill_ssdt_generator = generate_cpu_entries,
#endif
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
old mode 100644
new mode 100755
index e8616f0..812c2f5
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
+#include <bootstate.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -397,13 +398,6 @@ static const struct cpu_driver driver __cpu_driver = {
static const void *microcode_patch;
static int ht_disabled;
-static void pre_mp_init(void)
-{
- /* Setup MTRRs based on physical address size. */
- x86_setup_mtrrs_with_detect();
- x86_mtrr_check();
-}
-
static int get_cpu_count(void)
{
msr_t msr;
@@ -463,7 +457,11 @@ static void post_mp_init(void)
}
static const struct mp_ops mp_ops = {
- .pre_mp_init = pre_mp_init,
+ /*
+ * Skip Pre MP init MTRR programming to ensure FSP-S is running
+ * from cached region set during Post car stage.
+ */
+ .pre_mp_init = NULL,
.get_cpu_count = get_cpu_count,
.get_smm_info = smm_info,
.get_microcode_info = get_microcode_info,
@@ -474,8 +472,9 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
-void soc_init_cpus(device_t dev)
+static void soc_init_cpus(void *unused)
{
+ device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
struct bus *cpu_bus = dev->link_list;
if (mp_init_with_smm(cpu_bus, &mp_ops)) {
@@ -486,6 +485,13 @@ void soc_init_cpus(device_t dev)
configure_thermal_target();
}
+/* Ensure to re-program all MTRRs based on DRAM resource settings */
+static void soc_post_cpus_init(void *unused)
+{
+ if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
+ printk(BIOS_ERR, "MTRR programming failure\n");
+}
+
int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
{
msr_t msr;
@@ -498,3 +504,9 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
msr = rdmsr(MTRR_CAP_MSR);
return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1);
}
+
+/*
+ * Do CPU MP Init before FSP Silicon Init
+ */
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL);
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL);
\ No newline at end of file
diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
index 8df7796..f1a9e53 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,7 +29,6 @@
void soc_irq_settings(FSP_SIL_UPD *params);
void pch_enable_dev(device_t dev);
void soc_init_pre_device(void *chip_info);
-void soc_init_cpus(device_t dev);
const char *soc_acpi_name(struct device *dev);
int init_igd_opregion(igd_opregion_t *igd_opregion);
extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
index 0ae87f4..136c4f2 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,7 +29,6 @@
void mainboard_silicon_init_params(FSP_S_CONFIG *params);
void pch_enable_dev(device_t dev);
void soc_init_pre_device(void *chip_info);
-void soc_init_cpus(device_t dev);
void soc_irq_settings(FSP_SIL_UPD *params);
const char *soc_acpi_name(struct device *dev);
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