[coreboot-gerrit] New patch to review for coreboot: mainboard/google/snappy: Set PL2 override to 15000mW

[Harry Pan (harry.pan@intel.com)]

Harry Pan (harry.pan at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18283

-gerrit

commit dfe7358bcfced64520c63857fde25e557cfa1e2e
Author: Harry Pan <harry.pan at intel.com>
Date:   Thu Feb 2 15:42:25 2017 +0800

    mainboard/google/snappy: Set PL2 override to 15000mW
    
    This patch sets PL2 override value to 15W in RAPL registers.
    
    BUG=chrome-os-partner:62110
    BRANCH=reef
    TEST=Apply new firmware to evaluate Octane benchmark score.
    
    Change-Id: I51734051586753677129314b5273fb275c74f5d2
    Signed-off-by: Harry Pan <harry.pan at intel.com>
---
 src/mainboard/google/reef/variants/snappy/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 6d7c8ca..c83306d 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -53,6 +53,8 @@ chip soc/intel/apollolake
 	# current VR solution. Experiments show that SoC TDP max (6W) can
 	# be reached when RAPL PL1 is set to 12W.
 	register "tdp_pl1_override_mw" = "12000"
+	# Set RAPL PL2 to 15W.
+	register "tdp_pl2_override_mw" = "15000"
 
 	# Enable Audio Clock and Power gating
 	register "hdaudio_clk_gate_enable" = "1"