[coreboot-gerrit] Patch set updated for coreboot: NOT FOR MERGE: test ddr2 spd decode
Arthur Heymans (arthur@aheymans.xyz)
gerrit at coreboot.org
Thu Feb 2 18:57:00 CET 2017
Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18278
-gerrit
commit 6f58ad358a479147844ed2c82a7feeb5c84e24c2
Author: Arthur Heymans <arthur at aheymans.xyz>
Date: Wed Feb 1 23:02:17 2017 +0100
NOT FOR MERGE: test ddr2 spd decode
Change-Id: I3494009eec88eb31efd031a6da27fd1108131beb
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
src/device/Kconfig | 4 ++++
src/device/dram/Makefile.inc | 1 +
src/device/dram/ddr2.c | 2 +-
src/northbridge/intel/i945/Kconfig | 1 +
src/northbridge/intel/i945/raminit.c | 12 +++++++++++-
5 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index d1f5694..baa72c0 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -214,6 +214,10 @@ config SPD_CACHE
bool
default n
+config DDR2_SPD
+ bool
+ default n
+
config PCI
bool
default n
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
index 05f440b..dbe4412 100644
--- a/src/device/dram/Makefile.inc
+++ b/src/device/dram/Makefile.inc
@@ -1 +1,2 @@
romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c
+romstage-$(CONFIG_DDR2_SPD) += ddr2.c
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index aa51b50..4f257bc 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -385,7 +385,7 @@ int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd)
}
printram(" Supported CAS : 0x%x\n", dimm->cas_supported);
- cl = spd_get_msbs(dimm->cas_supported);
+ cl = spd_get_msbs(dimm->cas_supported) - 2;
dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]);
dimm->access_time[cl] = spd_decode_bcd_time(spd[10]);
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index efe192b..65be5a1 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -25,6 +25,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select VGA
select INTEL_GMA_ACPI
select RELOCATABLE_RAMSTAGE
+ select DDR2_SPD
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index cc227cc..e86ff17 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -28,6 +28,7 @@
#include "i945.h"
#include "chip.h"
#include <cbmem.h>
+#include <device/dram/ddr2.h>
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
@@ -315,7 +316,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
static void sdram_get_dram_configuration(struct sys_info *sysinfo)
{
u32 dimm_mask = 0;
- int i;
+ int i, j;
/**
* i945 supports two DIMMs, in two configurations:
@@ -360,6 +361,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
for (i = 0; i<(2 * DIMM_SOCKETS); i++) {
int device = get_dimm_spd_address(sysinfo, i);
u8 reg8;
+ spd_raw_data raw_spd;
+ dimm_attr *dimm = NULL;
/* Initialize the socket information with a sane value */
sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
@@ -375,6 +378,13 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
continue;
}
+ for (j = 0; j < 128; j++)
+ raw_spd[j] = spd_read_byte(device, j);
+ printk(BIOS_DEBUG, "Before spd_decode_ddr2\n");
+ spd_decode_ddr2(dimm, raw_spd);
+ printk(BIOS_DEBUG, "Before dram_print_spd_ddr2\n");
+ dram_print_spd_ddr2(dimm);
+
reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
if (reg8 == ERROR_SCHEME_ECC)
die("Error: ECC memory not supported by this chipset\n");
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