[coreboot-gerrit] Patch set updated for coreboot: google/eve: Fix DRAM DQS map

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18279

-gerrit

commit 2f7a5eedd99ac33ba6d1640c44d27a4e9f119e9b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Feb 1 16:37:29 2017 -0800

    google/eve: Fix DRAM DQS map
    
    This change fixes the two sets of pins that were swapped in the
    map of DQS signals from CPU to DRAM for channel 1.
    
    Although this does not appear to have any impact to the system it
    does result in different register values for DQS pin mapping that
    are programmed inside FSP.
    
    BUG=chrome-os-partner:58666
    TEST=This fix was verified against the current schematic and using
    FSP debug output.
    
    Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 3rdparty/blobs                      | 2 +-
 src/mainboard/google/eve/romstage.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index 8090bdd..9ba0703 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 8090bdd59853599e469b7503ea473ca12e8c681b
+Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1
diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c
index 4ae87fd..2378e90 100644
--- a/src/mainboard/google/eve/romstage.c
+++ b/src/mainboard/google/eve/romstage.c
@@ -32,7 +32,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	/* DQS CPU<>DRAM map */
 	const u8 dqs_map[2][8] = {
 		{ 1, 0, 2, 3, 4, 5, 6, 7 },
-		{ 1, 0, 4, 5, 3, 2, 7, 6 } };
+		{ 1, 0, 5, 4, 2, 3, 7, 6 } };
 	/* Rcomp resistor */
 	const u16 rcomp_resistor[] = { 200, 81, 162 };
 	/* Rcomp target */