[coreboot-gerrit] New patch to review for coreboot: NOT FOR MERGE: test ddr2 spd decode

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18278

-gerrit

commit e359ef9c71f59334ce3fea81975c9c7088da4ccd
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Wed Feb 1 23:02:17 2017 +0100

    NOT FOR MERGE: test ddr2 spd decode
    
    Change-Id: I3494009eec88eb31efd031a6da27fd1108131beb
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/device/Kconfig                   |  4 ++++
 src/device/dram/Makefile.inc         |  1 +
 src/device/dram/ddr2.c               |  4 ++--
 src/northbridge/intel/i945/Kconfig   |  1 +
 src/northbridge/intel/i945/raminit.c | 10 +++++++++-
 5 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/device/Kconfig b/src/device/Kconfig
index d1f5694..baa72c0 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -214,6 +214,10 @@ config SPD_CACHE
 	bool
 	default n
 
+config DDR2_SPD
+	bool
+	default n
+
 config PCI
 	bool
 	default n
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
index 05f440b..dbe4412 100644
--- a/src/device/dram/Makefile.inc
+++ b/src/device/dram/Makefile.inc
@@ -1 +1,2 @@
 romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c
+romstage-$(CONFIG_DDR2_SPD) += ddr2.c
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index e8791c7..7c9b2ed 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -205,7 +205,7 @@ static u32 spd_decode_tRR_time(u8 c)
  * Decodes a raw SPD data from a DDR2 DIMM.
  * Returns cycle time in 1/256th us.
  */
-static void spd_decode_tRPtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 tRFC)
+static void spd_decode_tRPtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 *tRFC)
 {
 	u8 b40, b41, b42;
 
@@ -385,7 +385,7 @@ int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd)
 	}
 	printram("  Supported CAS      : 0x%x\n", dimm->cas_supported);
 
-	cl = spd_get_msbs(dimm->cas_supported);
+	cl = spd_get_msbs(dimm->cas_supported) - 2;
 
 	dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]);
 	dimm->access_time[cl] = spd_decode_bcd_time(spd[10]);
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index efe192b..65be5a1 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -25,6 +25,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select VGA
 	select INTEL_GMA_ACPI
 	select RELOCATABLE_RAMSTAGE
+	select DDR2_SPD
 
 config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 	def_bool n
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index cc227cc..c84f90f 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -28,6 +28,7 @@
 #include "i945.h"
 #include "chip.h"
 #include <cbmem.h>
+#include <device/dram/ddr2.h>
 
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP
@@ -315,7 +316,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 {
 	u32 dimm_mask = 0;
-	int i;
+	int i, j;
 
 	/**
 	 * i945 supports two DIMMs, in two configurations:
@@ -360,6 +361,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 	for (i = 0; i<(2 * DIMM_SOCKETS); i++) {
 		int device = get_dimm_spd_address(sysinfo, i);
 		u8 reg8;
+		spd_raw_data raw_spd;
+		dimm_attr *dimm = NULL;
 
 		/* Initialize the socket information with a sane value */
 		sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
@@ -375,6 +378,11 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 			continue;
 		}
 
+		for (j = 0; j < 128; j++)
+			raw_spd[j] = spd_read_byte(device, j);
+		spd_decode_ddr2(dimm, raw_spd);
+		dram_print_spd_ddr2(dimm);
+
 		reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 		if (reg8 == ERROR_SCHEME_ECC)
 			die("Error: ECC memory not supported by this chipset\n");