[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Limit DDR3 speed to 400MHz

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22998


Change subject: nb/intel/x4x: Limit DDR3 speed to 400MHz
......................................................................

nb/intel/x4x: Limit DDR3 speed to 400MHz

Faster speeds seem to work much worse compatibility wise with this
code.

Change-Id: I11f663a50a42c70ed63ba045bd89fcd96cd047ce
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/x4x/spd_ddr3_decode.c
1 file changed, 1 insertion(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/22998/1

diff --git a/src/northbridge/intel/x4x/spd_ddr3_decode.c b/src/northbridge/intel/x4x/spd_ddr3_decode.c
index a57b14c..35d6bf6 100644
--- a/src/northbridge/intel/x4x/spd_ddr3_decode.c
+++ b/src/northbridge/intel/x4x/spd_ddr3_decode.c
@@ -86,6 +86,7 @@
 	}
 
 	min_tCLK = MAX(min_tCLK, saved_timings->min_tclk);
+	min_tCLK = TCK_400MHZ; /* TODO: other speedsseem to fail */
 	normalize_tCLK(&min_tCLK);
 	if (min_tCLK == 0) {
 		printk(BIOS_ERR, "DRAM frequency is under lowest supported "

-- 
To view, visit https://review.coreboot.org/22998
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I11f663a50a42c70ed63ba045bd89fcd96cd047ce
Gerrit-Change-Number: 22998
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20171226/9a6d0dfb/attachment.html>