[coreboot-gerrit] Change in coreboot[master]: src/sb/intel/common/pirq_gen: Fix some issues
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sat Dec 23 21:50:58 CET 2017
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22979
Change subject: src/sb/intel/common/pirq_gen: Fix some issues
......................................................................
src/sb/intel/common/pirq_gen: Fix some issues
A few thing that are fixed:
* Don't declare DEFAULT_RCBA redundantly.
* Only loop over PCI devices on bus 0
* Add a license header to rcba_pirq.c
* Remove inappropriate use of typedefs
Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/common/acpi_pirq_gen.c
M src/southbridge/intel/common/acpi_pirq_gen.h
M src/southbridge/intel/common/rcba_pirq.c
M src/southbridge/intel/common/rcba_pirq.h
6 files changed, 52 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22979/1
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index ed2b979..0ef1168 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -46,6 +46,10 @@
hex
default 0xfef00000
+config DEFAULT_RCBA
+ hex
+ default 0xfed1c000
+
config DRAM_RESET_GATE_GPIO
int
default 60
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 83d9d8d..0bb5306 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -46,9 +46,9 @@
#define DEFAULT_PMBASE 0x0500
#ifndef __ACPI__
-#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#define DEFAULT_RCBA ((u8 *)CONFIG_DEFAULT_RCBA)
#else
-#define DEFAULT_RCBA 0xfed1c000
+#define DEFAULT_RCBA CONFIG_DEFAUL_RCBA
#endif
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c
index 3ff591c..944b202 100644
--- a/src/southbridge/intel/common/acpi_pirq_gen.c
+++ b/src/southbridge/intel/common/acpi_pirq_gen.c
@@ -32,18 +32,14 @@
{
char buffer[DEVICE_PATH_MAX];
device_t dev;
- pci_pin_t prev_int_pin = PCI_INT_NONE;
+ u8 prev_int_pin_mask = 0;
u8 prev_pci_dev = 0;
size_t num_devs = 0;
- for (dev = all_devices; dev; dev = dev->next) {
+ for (dev = dev_find_slot(0, PCI_DEVFN(0, 0)); dev; dev = dev->sibling) {
u8 pci_dev;
u8 int_pin;
- pirq_t pirq;
-
- if (dev->path.type != DEVICE_PATH_PCI ||
- dev->bus->secondary != 0)
- continue;
+ enum pirq pirq;
pci_dev = PCI_SLOT(dev->path.pci.devfn);
int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);
@@ -53,19 +49,23 @@
pirq = intel_common_map_pirq(dev, int_pin);
if (emit == EMIT_NONE) /* Only print on the first pass */
- printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%d\n",
+ printk(BIOS_DEBUG, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%d\n",
dev_path(dev), int_pin, pirq);
if (pirq == PIRQ_NONE)
continue;
/* Avoid duplicate entries */
- if (prev_pci_dev == pci_dev && prev_int_pin == int_pin) {
- continue;
+ if (prev_pci_dev == pci_dev) {
+ if (prev_int_pin_mask & (1 << int_pin)) {
+ continue;
+ }
+ prev_int_pin_mask |= (1 << int_pin);
} else {
- prev_int_pin = int_pin;
+ prev_int_pin_mask = 0;
prev_pci_dev = pci_dev;
}
+
if (emit != EMIT_NONE) {
acpigen_write_package(4);
acpigen_write_dword((pci_dev << 16) | 0xffff);
@@ -87,13 +87,15 @@
return num_devs;
}
-void intel_acpi_gen_def_acpi_pirq(device_t dev)
+void intel_acpi_gen_def_acpi_pirq(struct device *dev)
{
const char *lpcb_path = acpi_device_path(dev);
const size_t num_devs = enumerate_root_pci_pins(EMIT_NONE, lpcb_path);
- if (!lpcb_path)
- die("ACPI_PIRQ_GEN: Missing LPCB ACPI path\n");
+ if (!lpcb_path) {
+ printk(BIOS_ERR,"ACPI_PIRQ_GEN: Missing LPCB ACPI path\n");
+ return;
+ }
acpigen_write_scope("\\_SB.PCI0");
acpigen_write_method("_PRT", 0);
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h
index bd702da..9fdee1a 100644
--- a/src/southbridge/intel/common/acpi_pirq_gen.h
+++ b/src/southbridge/intel/common/acpi_pirq_gen.h
@@ -16,15 +16,15 @@
#ifndef INTEL_COMMON_ACPI_PIRQ_GEN_H
#define INTEL_COMMON_ACPI_PIRQ_GEN_H
-typedef enum pci_pin {
+enum pci_pin {
PCI_INT_NONE = 0,
PCI_INT_A,
PCI_INT_B,
PCI_INT_C,
PCI_INT_D,
-} pci_pin_t;
+};
-typedef enum pirq {
+enum pirq {
PIRQ_NONE = 0,
PIRQ_A,
PIRQ_B,
@@ -34,9 +34,10 @@
PIRQ_F,
PIRQ_G,
PIRQ_H,
-} pirq_t;
+};
-void intel_acpi_gen_def_acpi_pirq(device_t dev);
-enum pirq intel_common_map_pirq(const device_t dev, const pci_pin_t pci_pin);
+void intel_acpi_gen_def_acpi_pirq(struct device *dev);
+enum pirq intel_common_map_pirq(const struct device *dev,
+ const enum pci_pin pci_pin);
#endif
diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c
index 1861154..6bed9ee 100644
--- a/src/southbridge/intel/common/rcba_pirq.c
+++ b/src/southbridge/intel/common/rcba_pirq.c
@@ -1,3 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur at aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -12,31 +27,28 @@
D26IR, D27IR, D28IR, D29IR, D30IR, D31IR,
};
-enum pirq intel_common_map_pirq(const device_t dev, const pci_pin_t pci_pin)
+enum pirq intel_common_map_pirq(const struct device *dev,
+ const enum pci_pin pci_pin)
{
u8 slot = PCI_SLOT(dev->path.pci.devfn);
u8 shift = 4 * (pci_pin - PCI_INT_A);
u8 pirq;
u16 reg;
- if (pci_pin < 1 || pci_pin > 4) {
+ if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) {
printk(BIOS_ERR, "Slot %d PCI pin %d out of bounds\n",
slot, pci_pin);
return PIRQ_NONE;
}
- if (slot < MIN_SLOT || slot > MAX_SLOT) {
+ if (slot < MIN_SLOT || slot > MAX_SLOT || slot == 24) {
/* non-PCH devices use 1:1 mapping. */
return pci_pin;
}
reg = pirq_dir_route_reg[slot - MIN_SLOT];
- pirq = ((RCBA16(reg) >> shift) & 0xf);
- if (pirq > 8) {
- printk(BIOS_ERR, "Reg 0x%04x PIRQ %c out of bounds\n",
- reg, 'A' + pirq);
- return PIRQ_NONE;
- }
- return PIRQ_A + pirq;
+ pirq = (RCBA16(reg) >> shift) & 0x7;
+
+ return (enum pirq)(PIRQ_A + pirq);
}
diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h
index cf76fb3..8158079 100644
--- a/src/southbridge/intel/common/rcba_pirq.h
+++ b/src/southbridge/intel/common/rcba_pirq.h
@@ -37,8 +37,6 @@
#define D20IR 0x3160 /* 16bit */
#define D19IR 0x3168 /* 16bit */
-#define DEFAULT_RCBA 0xfed1c000
-
-#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x))))
+#define RCBA16(x) (*((volatile u16 *)(CONFIG_DEFAULT_RCBA + (x))))
#endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d
Gerrit-Change-Number: 22979
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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