[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Program DMI PCR settings
Lijian Zhao (Code Review)
gerrit at coreboot.org
Thu Dec 21 22:42:36 CET 2017
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22970
Change subject: soc/intel/cannonlake: Program DMI PCR settings
......................................................................
soc/intel/cannonlake: Program DMI PCR settings
According to CNL PCH BIOS spec(570374) 2.4.1, DMI cycle decoding need
to be programmed before it got locked. Update lpc programming to add
decode programming in DMI side as well.
BUG=b.70765863
TEST=Apply changes and add chromeos EC decoding in mainboard ec.c, read
back IO port in depthcharge cli and return is not zero.
Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/lpc.c
3 files changed, 34 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/22970/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 61318a4..91782ba 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -16,6 +16,7 @@
bootblock-y += gpio.c
bootblock-y += gspi.c
bootblock-y += i2c.c
+bootblock-y += lpc.c
bootblock-y += memmap.c
bootblock-y += spi.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 0deece6..8eda152 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -16,6 +16,7 @@
#include <device/device.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
#include <intelblocks/smbus.h>
@@ -37,11 +38,6 @@
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
-#define PCR_DMI_LPCLGIR1 0x2730
-#define PCR_DMI_LPCLGIR2 0x2734
-#define PCR_DMI_LPCLGIR3 0x2738
-#define PCR_DMI_LPCLGIR4 0x273c
-
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
@@ -49,9 +45,6 @@
#define PCR_DMI_TCOBASE 0x2778
#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */
-#define PCR_DMI_LPCIOD 0x2770
-#define PCR_DMI_LPCIOE 0x2774
-
static void enable_p2sbbar(void)
{
device_t dev = PCH_DEV_P2SB;
@@ -176,6 +169,9 @@
dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN;
pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
+
+ /* Program generic IO Decode Range */
+ pch_enable_lpc();
}
void pch_early_init(void)
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index e906d99..45bda7c 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -30,6 +30,7 @@
#include <intelblocks/pcr.h>
#include <reg_script.h>
#include <soc/iomap.h>
+#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
@@ -48,6 +49,32 @@
return cnl_lpc_fixed_mmio_ranges;
}
+void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
+{
+ const config_t *config = dev->chip_info;
+
+ gen_io_dec[0] = config->gen1_dec;
+ gen_io_dec[1] = config->gen2_dec;
+ gen_io_dec[2] = config->gen3_dec;
+ gen_io_dec[3] = config->gen4_dec;
+}
+
+void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
+{
+ uint16_t lpc_en;
+
+ /* Mirror these same settings in DMI PCR */
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
+
+ /* LPC IO Decode Enable */
+ lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_EN);
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en);
+}
+
+#if ENV_RAMSTAGE
static void pch_enable_ioapic(const struct device *dev)
{
u32 reg32;
@@ -70,27 +97,6 @@
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
-
-void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
-{
- const config_t *config = dev->chip_info;
-
- gen_io_dec[0] = config->gen1_dec;
- gen_io_dec[1] = config->gen2_dec;
- gen_io_dec[2] = config->gen3_dec;
- gen_io_dec[3] = config->gen4_dec;
-}
-
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
-
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@@ -204,3 +210,5 @@
i8259_configure_irq_trigger(9, 1);
clock_gate_8254(dev);
}
+#endif
+
--
To view, visit https://review.coreboot.org/22970
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3
Gerrit-Change-Number: 22970
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20171221/dea0a50c/attachment.html>
More information about the coreboot-gerrit
mailing list