[coreboot-gerrit] Change in coreboot[master]: nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/22957


Change subject: nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce
......................................................................

nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce

Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/include/cpu/x86/tsc.h
M src/northbridge/intel/fsp_rangeley/udelay.c
2 files changed, 3 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/22957/1

diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 4cf4fbc..35c8a82 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -11,6 +11,8 @@
 #define TSC_SYNC
 #endif
 
+#define MSR_PLATFORM_INFO 0xce
+
 struct tsc_struct {
 	unsigned int lo;
 	unsigned int hi;
diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c
index 5aca229..01989ab 100644
--- a/src/northbridge/intel/fsp_rangeley/udelay.c
+++ b/src/northbridge/intel/fsp_rangeley/udelay.c
@@ -43,7 +43,7 @@
 	u32 fsb = 100, divisor;
 	u32 d;			/* ticks per us */
 
-	msr = rdmsr(0xce);
+	msr = rdmsr(MSR_PLATFORM_INFO);
 	divisor = (msr.lo >> 8) & 0xff;
 
 	d = fsb * divisor;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089
Gerrit-Change-Number: 22957
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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