[coreboot-gerrit] Change in coreboot[master]: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/22954 )

Change subject: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL
......................................................................

soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL

Even though kaby lake and cannon lake are using the same GSPI
controller, bit meanings (for polarity and state) in SPI_CS_CONTROL
register are significantly different. This change provides and uses
SoC-specific callbacks to identify the right bits to be used for
polarity and state while programming the SPI_CS_CONTROL register.

BUG=b:70628116

Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8
Signed-off-by: Furquan Shaikh <furquan at google.com>
---
M src/soc/intel/cannonlake/gspi.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/common/block/include/intelblocks/gspi.h
M src/soc/intel/skylake/gspi.c
4 files changed, 102 insertions(+), 32 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/22954/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8
Gerrit-Change-Number: 22954
Gerrit-PatchSet: 2
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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