[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDS

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22840


Change subject: soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDS
......................................................................

soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDS

TEST=System is able to power on after reconnecting power system.

Change-Id: I41e655fe79d958cce9e627ea2f2380185364ab19
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/include/soc/pm.h
M src/soc/intel/cannonlake/pmc.c
2 files changed, 30 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/22840/1

diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h
index 378fac9..d92d4f4 100644
--- a/src/soc/intel/cannonlake/include/soc/pm.h
+++ b/src/soc/intel/cannonlake/include/soc/pm.h
@@ -140,6 +140,10 @@
 #define ENABLE_SMI_PARAMS \
 	(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
 
+#define MAINBOARD_POWER_OFF	0
+#define MAINBOARD_POWER_ON	1
+#define MAINBOARD_POWER_KEEP	2
+
 #define	PSS_RATIO_STEP		2
 #define	PSS_MAX_ENTRIES		8
 #define	PSS_LATENCY_TRANSITION	10
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index 6ec4d38..68b2325 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -25,6 +25,32 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 
+/*
+ * Determines what state to go to when power is reapplied
+ * after a power failure (G3 State)
+ */
+static void pmc_set_afterg3(int s5pwr)
+{
+	uint32_t reg32;
+	uint8_t *pmcbase = pmc_mmio_regs();
+
+	reg32 = read32(pmcbase + GEN_PMCON_A);
+	if (s5pwr == MAINBOARD_POWER_ON)
+		reg32 &= ~1;
+	else
+		reg32 |= 1;
+	write32(pmcbase + GEN_PMCON_A, reg32);
+}
+
+/*
+ * Set PMC register to know which state system should be after
+ * power reapplied
+ */
+void pmc_soc_restore_power_failiure(void)
+{
+	pmc_set_afterg3(MAINBOARD_POWER_ON);
+}
+
 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
 {
 	uint32_t reg;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I41e655fe79d958cce9e627ea2f2380185364ab19
Gerrit-Change-Number: 22840
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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