[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add API to restore power failure into PMC common code

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22838


Change subject: soc/intel/common: Add API to restore power failure into PMC common code
......................................................................

soc/intel/common: Add API to restore power failure into PMC common code

PMC config register need to program to define which state system
should be after reapplied power from G3 state.

0 = System will return to S0 state
1 = System will return to S5 state

Refer to EDS for detailed programming sequence.

Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 18 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/22838/1

diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index a045bbe..38169de 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -133,6 +133,12 @@
 void pmc_clear_prsts(void);
 
 /*
+ * Set PMC register to know which state system should be after
+ * power reapplied
+ */
+void pmc_soc_restore_power_failiure(void);
+
+/*
  * Enable or disable global reset. If global reset is enabled, hard reset and
  * soft reset will trigger global reset, where both host and TXE are reset.
  * This is cleared on cold boot, hard reset, soft reset and Sx.
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index f653bf0..9c64ba2 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -80,6 +80,18 @@
 	return generic_sts;
 }
 
+/*
+ * Set PMC register to know which state system should be after
+ * power reapplied
+ */
+__attribute__ ((weak)) void pmc_soc_restore_power_failiure(void)
+{
+	/*
+	 * SoC code should set PMC config register in order to set
+	 * MAINBOARD_POWER_ON bit as per EDS.
+	 */
+}
+
 static uint32_t pmc_reset_smi_status(void)
 {
 	uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02
Gerrit-Change-Number: 22838
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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