[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22781


Change subject: soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock
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soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock

This change adds a call to gspi_early_bar_init in bootblock to
allocate a temporary BAR for any GSPI buses that are accessed before
resource allocation is done in ramstage.

Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/cannonlake/bootblock/pch.c
1 file changed, 2 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/22781/1

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 0deece6..c69fffa 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -16,6 +16,7 @@
 
 #include <device/device.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/gspi.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/smbus.h>
@@ -97,6 +98,7 @@
 void bootblock_pch_early_init(void)
 {
 	fast_spi_early_init(SPI_BASE_ADDRESS);
+	gspi_early_bar_init();
 	enable_p2sbbar();
 	/*
 	 * Enabling PWRM Base for accessing

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146
Gerrit-Change-Number: 22781
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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