[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add support for D0 stepping

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22676


Change subject: soc/intel/cannonlake: Add support for D0 stepping
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soc/intel/cannonlake: Add support for D0 stepping

D0 stepping with CPUID 0x60663 need to be added in coreboot.

TEST=Boot up with D0 stepping processor

Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/include/soc/cpu.h
M src/soc/intel/common/block/include/intelblocks/mp_init.h
2 files changed, 2 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22676/1

diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h
index bd9db37..e50801f 100644
--- a/src/soc/intel/cannonlake/include/soc/cpu.h
+++ b/src/soc/intel/cannonlake/include/soc/cpu.h
@@ -25,6 +25,7 @@
 #define CPUID_CANNONLAKE_A0	0x60660
 #define CPUID_CANNONLAKE_B0	0x60661
 #define CPUID_CANNONLAKE_C0	0x60662
+#define CPUID_CANNONLAKE_D0	0x60663
 
 /* Latency times in units of 1024ns. */
 #define C_STATE_LATENCY_CONTROL_0_LIMIT	0x4e
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index ab3e1ed..3057209 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -31,6 +31,7 @@
 #define CPUID_CANNONLAKE_A0	0x60660
 #define CPUID_CANNONLAKE_B0	0x60661
 #define CPUID_CANNONLAKE_C0	0x60662
+#define CPUID_CANNONLAKE_D0	0x60663
 #define CPUID_APOLLOLAKE_A0	0x506c8
 #define CPUID_APOLLOLAKE_B0	0x506c9
 #define CPUID_APOLLOLAKE_E0	0x506ca

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931
Gerrit-Change-Number: 22676
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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