[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Add SGX support
Pratikkumar V Prajapati (Code Review)
gerrit at coreboot.org
Tue Aug 29 23:35:54 CEST 2017
Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21276
Change subject: soc/intel/apollolake: Add SGX support
......................................................................
soc/intel/apollolake: Add SGX support
- Call into commmon SGX code to configure core PRMRR
and follow other SGX init seqeuence.
- Report correct cbmem top with PRMRR enabled
- Enable SOC_INTEL_COMMON_BLOCK_SGX for both APL/GLK, so that
build does not break.
- Enable SOC_INTEL_COMMON_BLOCK_CPU_MPINIT for GLK, as MP init needs
to be completed before calling into fsp-s for SGX.
Change-Id: I9331cf5b2cbc86431e2749b84a55f77f7f3c5960
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
4 files changed, 38 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/21276/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 5ff328b..7e13abf 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -7,6 +7,7 @@
bool
default n
select SOC_INTEL_APOLLOLAKE
+ select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
help
Intel GLK support
@@ -77,6 +78,7 @@
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS
+ select SOC_INTEL_COMMON_BLOCK_SGX
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XDCI
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e860daa..9e2b310 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -98,6 +98,7 @@
ramstage-y += gpio_apl.c
endif
+CPPFLAGS_common += -I$(src)/soc/intel/apollolake
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
ifeq ($(CONFIG_SOC_INTEL_GLK),y)
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 98cd23a..7b041c6 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2015-2017 Intel Corp.
* (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
* (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
*
@@ -32,6 +32,7 @@
#include <intelblocks/fast_spi.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
+#include <intelblocks/sgx.h>
#include <intelblocks/smm.h>
#include <reg_script.h>
#include <romstage_handoff.h>
@@ -62,6 +63,12 @@
void soc_core_init(device_t cpu)
{
+ /* Clear out pending MCEs */
+ /* TODO(adurbin): This should only be done on a cold boot. Also, some
+ * of these banks are core vs package scope. For now every CPU clears
+ * every bank. */
+ mca_configure();
+
/* Set core MSRs */
reg_script_run(core_msr_script);
/*
@@ -70,6 +77,9 @@
* implemented in microcode.
*/
enable_pm_timer_emulation();
+
+ /* Configure Core PRMRR for SGX. */
+ prmrr_core_configure();
}
#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
@@ -213,6 +223,13 @@
* the microcode on all cores before releasing them from reset. That means that
* the BSP and all APs will come up with the same microcode revision.
*/
+
+static void post_mp_init(void)
+{
+ smm_southbridge_enable();
+ mp_run_on_all_cpus(sgx_configure, 2000);
+}
+
static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init,
.get_cpu_count = get_cpu_count,
@@ -220,7 +237,7 @@
.get_microcode_info = get_microcode_info,
.pre_mp_smm_init = smm_southbridge_clear_state,
.relocation_handler = relocation_handler,
- .post_mp_init = smm_southbridge_enable,
+ .post_mp_init = post_mp_init,
};
void soc_init_cpus(struct bus *cpu_bus)
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index c54423c..87546f6 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2017 Intel Corp.
* (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -26,8 +26,10 @@
#include <arch/io.h>
#include <assert.h>
#include <cbmem.h>
+#include <chip.h>
#include <device/pci.h>
#include <fsp/memmap.h>
+#include <fsp/util.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
@@ -45,7 +47,19 @@
void *cbmem_top(void)
{
- return (void *)smm_region_start();
+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ assert(dev != NULL);
+ const config_t *config = dev->chip_info;
+ void *smm_start = (void *)smm_region_start();
+ void *tolum;
+ tolum = smm_start;
+
+ /* FSP allocates 2x PRMRR Size Memory for alignment */
+ if (config->sgx_enable)
+ tolum = smm_start - ((config->PrmrrSize) << 1);
+
+ printk(BIOS_SPEW, "cbmem_top = 0x%p\n", tolum);
+ return tolum;
}
void smm_region(void **start, size_t *size)
--
To view, visit https://review.coreboot.org/21276
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9331cf5b2cbc86431e2749b84a55f77f7f3c5960
Gerrit-Change-Number: 21276
Gerrit-PatchSet: 1
Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
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