[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/sgx: use SOC specific APIs to get PRMRR base and mask

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21246


Change subject: soc/intel/common/sgx: use SOC specific APIs to get PRMRR base and mask
......................................................................

soc/intel/common/sgx: use SOC specific APIs to get PRMRR base and mask

Use soc_get_uncore_prmmr_base() and soc_get_uncore_prmmr_msk()
to get PRMRR base and mask respectively

Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
---
M src/soc/intel/common/block/sgx/sgx.c
1 file changed, 17 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/21246/1

diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index da84ea6..a199a83 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -21,6 +21,7 @@
 #include <cpu/intel/microcode.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/sgx.h>
+#include <intelblocks/systemagent.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -48,13 +49,27 @@
 
 	/* PRMRR base and mask are read from the UNCORE PRMRR MSRs
 	 * that are already set in FSP-M. */
-	prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
-	prmrr_mask = rdmsr(UNCORE_PRMRR_PHYS_MASK_MSR);
+	if (soc_get_uncore_prmmr_base(&prmrr_base) < 0) {
+		printk(BIOS_ERR, "SGX: Failed to read UNCORE PRMRR base\n");
+		return;
+	}
+
 	if (!prmrr_base.lo) {
 		printk(BIOS_ERR, "SGX Error: Uncore PRMRR is not set!\n");
 		return;
 	}
 
+	printk(BIOS_INFO, "SGX: prmrr_base.hi = 0x%x\n", prmrr_base.hi);
+	printk(BIOS_INFO, "SGX: prmrr_base.lo = 0x%x\n", prmrr_base.lo);
+
+	if (soc_get_uncore_prmmr_mask(&prmrr_mask) < 0) {
+		printk(BIOS_ERR, "SGX: Failed to read UNCORE PRMRR mask\n");
+		return;
+	}
+
+	printk(BIOS_INFO, "SGX: prmrr_mask.hi = 0x%x\n", prmrr_mask.hi);
+	printk(BIOS_INFO, "SGX: prmrr_mask.lo = 0x%x\n", prmrr_mask.lo);
+
 	msr = rdmsr(PRMRR_PHYS_MASK_MSR);
 	/* If it is locked don't attempt to write PRMRR MSRs. */
 	if (msr.lo & PRMRR_PHYS_MASK_LOCK)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646
Gerrit-Change-Number: 21246
Gerrit-PatchSet: 1
Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
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