[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Populate NVS SCC BAR1

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21172


Change subject: soc/intel/braswell: Populate NVS SCC BAR1
......................................................................

soc/intel/braswell: Populate NVS SCC BAR1

Cherry-pick from Chromium commit f92d7be.

This BAR is used in _PS0 and _PS3 methods and is used by kernel driver to put
SD controller in D3

Original-Change-Id: Iae4722cb222f61e96948265f57d6b522065853d9
Original-Signed-off-by: Hannah Williams <hannah.williams at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie at google.com>
Original-Tested-by: Aseda Aboagye <aaboagye at chromium.org>

Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/braswell/scc.c
1 file changed, 4 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21172/1

diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index 3172b73..6538c5c 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -42,7 +42,10 @@
 	/* Save BAR0 and BAR1 to ACPI NVS */
 	bar = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (bar)
-		gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base;
+		gnvs->dev.scc_bar0[nvs_index] = bar->base;
+	bar = find_resource(dev, PCI_BASE_ADDRESS_2);
+	if (bar)
+		gnvs->dev.scc_bar1[nvs_index] = bar->base;
 
 	/* Device is enabled in ACPI mode */
 	gnvs->dev.scc_en[nvs_index] = 1;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab
Gerrit-Change-Number: 21172
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
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