[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Put SERIRQ in quiet mode

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21173


Change subject: soc/intel/braswell: Put SERIRQ in quiet mode
......................................................................

soc/intel/braswell: Put SERIRQ in quiet mode

Cherry-pick from Chromium commit 1568761.

Original-Change-Id: If459c3cab8fb7ca13d8bff3173a94855ec2e2810
Original-Signed-off-by: Hannah Williams <hannah.williams at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Tested-by: Kevin K Wong <kevin.k.wong at intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie at google.com>
Original-Tested-by: Aseda Aboagye <aaboagye at chromium.org>

Change-Id: Ibb2e6d316adcfcc0d56d242501aac9c4c0bbdf62
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/braswell/include/soc/lpc.h
M src/soc/intel/braswell/southcluster.c
2 files changed, 16 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21173/1

diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h
index 93ece3d..d842274 100644
--- a/src/soc/intel/braswell/include/soc/lpc.h
+++ b/src/soc/intel/braswell/include/soc/lpc.h
@@ -30,6 +30,9 @@
 #define UART_CONT	0x80
 #define RCBA		0xf0
 
+/* Memory Mapped IO in LPC bridge */
+#define SCNT		0x10
+#define SCNT_MODE	(1 << 7) /* When cleared, SERIRQ is in quiet mode */
 
 #define RID_A_STEPPING_START 1
 #define RID_B_STEPPING_START 5
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 0e2d5e2..e033123 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -38,6 +38,18 @@
 #include <soc/spi.h>
 #include <spi-generic.h>
 #include <stdint.h>
+#include <reg_script.h>
+
+static const struct reg_script ops[] = {
+	REG_MMIO_RMW32(ILB_BASE_ADDRESS + SCNT,
+		~SCNT_MODE, 0),	/* put LPC SERIRQ in Quiet Mode */
+	REG_SCRIPT_END
+};
+
+static void enable_serirq_quiet_mode(void)
+{
+	reg_script_run(ops);
+}
 
 static inline void
 add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
@@ -503,6 +515,7 @@
 		write32(spi + LVSCC, cfg.lvscc | VCL);
 	}
 	spi_init();
+	enable_serirq_quiet_mode();
 
 	printk(BIOS_DEBUG, "Finalizing SMM.\n");
 	outb(APM_CNT_FINALIZE, APM_CNT);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibb2e6d316adcfcc0d56d242501aac9c4c0bbdf62
Gerrit-Change-Number: 21173
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
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