[coreboot-gerrit] Change in coreboot[master]: google/cyan: Disable unused lines on Gpio North Bank

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21168


Change subject: google/cyan: Disable unused lines on Gpio North Bank
......................................................................

google/cyan: Disable unused lines on Gpio North Bank

Cherry-pick from Chromium commit 1940eb6.

The unused lines leads to spurious interrupts on few of the systems.

Original-Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-by: Bernie Thompson <bhthompson at chromium.org>
Original-Tested-by: Bernie Thompson <bhthompson at chromium.org>

Change-Id: I6f4f7cec8ef11e781c66b6efff4188259469e41c
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/google/cyan/gpio.c
1 file changed, 10 insertions(+), 12 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21168/1

diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c
index 66c7c2a..a3883391 100644
--- a/src/mainboard/google/cyan/gpio.c
+++ b/src/mainboard/google/cyan/gpio.c
@@ -149,16 +149,15 @@
 
 /* North Community */
 static const struct soc_gpio_map  gpn_gpio_map[] = {
-	Native_M5, /* 00 GPIO_DFX0 */
-	Native_M5, /* 01 GPIO_DFX3 */
-	Native_M1, /* 02 GPIO_DFX7 */
-	Native_M5, /* 03 GPIO_DFX1 */
-	Native_M1, /* 04 GPIO_DFX5 */
-	Native_M1, /* 05 GPIO_DFX4 */
-	GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA),
-	/* 06 GPIO_DFX8 */
-	Native_M5, /* 07 GPIO_DFX2 */
-	Native_M8, /* 08 GPIO_DFX6 */
+	GPIO_NC, /* 00 GPIO_DFX0 */
+	GPIO_NC, /* 01 GPIO_DFX3 */
+	GPIO_NC, /* 02 GPIO_DFX7 */
+	GPIO_NC, /* 03 GPIO_DFX1 */
+	GPIO_NC, /* 04 GPIO_DFX5 */
+	GPIO_NC, /* 05 GPIO_DFX4 */
+	GPIO_NC, /* 06 GPIO_DFX8 */
+	GPIO_NC, /* 07 GPIO_DFX2 */
+	GPIO_NC, /* 08 GPIO_DFX6 */
 	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
@@ -169,8 +168,7 @@
 	GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
 	/* 19 GPIO_SUS1 */
 	GPIO_NC, /* 20 GPIO_SUS5 */
-	GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA),
-	/* 21 SEC_GPIO_SUS11 */
+	GPIO_NC, /* 21 SEC_GPIO_SUS11 */
 	GPIO_NC, /* 22 GPIO_SUS4 */
 	GPIO_NC,
 	/* 23 SEC_GPIO_SUS8 */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6f4f7cec8ef11e781c66b6efff4188259469e41c
Gerrit-Change-Number: 21168
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
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