[coreboot-gerrit] Change in coreboot[master]: google/cyan: Support reading Memory strap GPIOs to select SPD

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21166


Change subject: google/cyan: Support reading Memory strap GPIOs to select SPD
......................................................................

google/cyan: Support reading Memory strap GPIOs to select SPD

Cherry-pick from Chromium commit 8f63720.

SoC GPIO to read Memory strap not getting configured
correctly causing incorrect RAMID read during ROMSTAGE

TEST=Build and boot the platform with differnt Memory type and
read RAMID correctly inside spd.c
RAMID = 0 => 4GB Samsung Memory
RAMID = 1 => 4GB Hynix Memory
RAMID = 2 => 2GB Samsung Memory
RAMID = 3 => 2GB Hynix Memory

Original-Change-Id: Ide9d4b5f73565cddd74cedf7afe4b7d168dde74c
Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>

Change-Id: If2ba9ec5be111b9c30360ffde41a2c644a69ecae
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/google/cyan/spd/spd.c
1 file changed, 14 insertions(+), 19 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/21166/1

diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index c2e9e79..a87aaae 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -17,6 +17,7 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <gpio.h>
 #include <lib.h>
 #include <memory_info.h>
 #include <smbios.h>
@@ -26,10 +27,6 @@
 #include <string.h>
 
 #define SPD_SIZE 256
-#define SATA_GP3_PAD_CFG0       0x5828
-#define I2C3_SCL_PAD_CFG0       0x5438
-#define MF_PLT_CLK1_PAD_CFG0    0x4410
-#define I2C3_SDA_PAD_CFG0       0x5420
 
 /*
  * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
@@ -39,22 +36,18 @@
  */
 static const uint32_t dual_channel_config = (1 << 0) | (1 << 1);
 
-static void configure_ramid_gpios(void)
-{
-	write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + SATA_GP3_PAD_CFG0),
-		(PAD_PULL_DISABLE | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));
-	write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + MF_PLT_CLK1_PAD_CFG0),
-		(PAD_PULL_DISABLE | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));
-}
-
 static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
 {
 	int ram_id = 0;
-	ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0;
-	ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1;
-	ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0)
-		<< 2;
-	ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3;
+
+	gpio_t spd_gpios[] = {
+		GP_SW_80,	/* SATA_GP3,RAMID0 */
+		GP_SW_67,	/* I2C3_SCL,RAMID1 */
+		GP_SE_02,	/* MF_PLT_CLK1, RAMID2 */
+		GP_SW_64,	/* I2C3_SDA RAMID3 */
+	};
+
+	ram_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 	printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
 	if (ram_id >= total_spds)
 		return NULL;
@@ -66,10 +59,14 @@
 	/* Display the RAM type */
 	switch (ram_id) {
 	case 0:
+		printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646Q-HYK0 1600MHz\n");
+		break;
 	case 2:
 		printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n");
 		break;
 	case 1:
+		printk(BIOS_DEBUG, "4GiB Hynix  H5TC4G63CFR-PBA 1600MHz\n");
+		break;
 	case 3:
 		printk(BIOS_DEBUG, "2GiB Hynix  H5TC4G63CFR-PBA 1600MHz\n");
 		break;
@@ -95,8 +92,6 @@
 
 	if (spd_file_len < SPD_SIZE)
 		die("Missing SPD data.");
-
-	configure_ramid_gpios();
 
 	/*
 	 * Both channels are always present in SPD data. Always use matched

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If2ba9ec5be111b9c30360ffde41a2c644a69ecae
Gerrit-Change-Number: 21166
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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