[coreboot-gerrit] Change in coreboot[master]: src/mainboard/intel/cannonlake: Add gpio support for cannonlake

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/21139 )

Change subject: src/mainboard/intel/cannonlake: Add gpio support for cannonlake
......................................................................


Patch Set 1:

(7 comments)

https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/chromeos.c
File src/mainboard/intel/cannonlake_rvp/chromeos.c:

https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/chromeos.c@21
PS1, Line 21: #include <vendorcode/google/chromeos/chromeos.h>
            : 
            : #include <variant/gpio.h>
order?


https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
File src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c:

https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c@24
PS1, Line 24:         /* A1  : ESPI_IO_0 */
            :         /* A2  : ESPI_IO_1 */
            :         /* A3  : ESPI_IO_2 */
            :         /* A4  : ESPI_IO_3 */
            :         /* A5  : ESPI_CSB */
            :         /* A6  : SERIRQ */
tabs at beginning.


https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c@30
PS1, Line 30: /* A7  : PRIQAB_GSP10_CS1B */
            : 	PAD_CFG_GPI_ACPI_SCI(GPP_A7, 20K_PU, PLTRST, NONE),
i think you should put the comment after macro for the same pin.

e.g.
PAD_CFG_GPI_ACPI_SCI(GPP_A7, 20K_PU, PLTRST, NONE), /* A7  : PRIQAB_GSP10_CS1B */


https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c@71
PS1, Line 71: 	/* B6  : SRCCLKREQB_1 */ 
            : 	/* B7  : SRCCLKREQB_2 */ 
            : 	/* B8  : SRCCLKREQB_3 */ 
            : 	/* B9  : SRCCLKREQB_4 */ 
            : 	/* B10 : SRCCLKREQB_5 */ 
            : 	/* B11 : EXT_PWR_GATEB */
white chars at end of line


https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c@133
PS1, Line 133: 	
remove extra tab


https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c@261
PS1, Line 261: 	
white char


https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h
File src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h:

https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h@23
PS1, Line 23: /* 
            :  * The next set of functions return the gpio table and fill in the number of
            :  * entries for each table. 
            :  */
/* The next set of functions return the gpio table and fill in the number of
 * entries for each table. */



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc
Gerrit-Change-Number: 21139
Gerrit-PatchSet: 1
Gerrit-Owner: John Zhao <john.zhao at intel.corp-partner.google.com>
Gerrit-Reviewer: John Zhao <john.zhao at intel.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Tue, 22 Aug 2017 05:11:29 +0000
Gerrit-HasComments: Yes
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