[coreboot-gerrit] Change in coreboot[master]: google/cyan: convert to variant configuration
Matt DeVillier (Code Review)
gerrit at coreboot.org
Mon Aug 21 07:48:08 CEST 2017
Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21126
Change subject: google/cyan: convert to variant configuration
......................................................................
google/cyan: convert to variant configuration
Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits.
This commit keeps code common to all Google Braswell boards in
the cyan baseboard, separates out the board-specific bits into
the new cyan variant, and defines the I2C ACPI devices such that
they can be easily reused for other variants. It also switches
the trackpad/touchscreen interrupts from edge to level, for
better performance/compatibility as was done with all previous
Google boards.
Additionally, a few hardcoded values were replaced with variables,
and a few typos/formatting errors were corrected.
Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/google/cyan/Kconfig
M src/mainboard/google/cyan/Kconfig.name
M src/mainboard/google/cyan/Makefile.inc
A src/mainboard/google/cyan/acpi/codec_maxim.asl
M src/mainboard/google/cyan/acpi/dptf.asl
M src/mainboard/google/cyan/acpi/mainboard.asl
M src/mainboard/google/cyan/acpi/superio.asl
A src/mainboard/google/cyan/acpi/touchscreen_elan.asl
A src/mainboard/google/cyan/acpi/trackpad_elan.asl
M src/mainboard/google/cyan/board_info.txt
M src/mainboard/google/cyan/boardid.c
M src/mainboard/google/cyan/ramstage.c
M src/mainboard/google/cyan/smihandler.c
R src/mainboard/google/cyan/variants/cyan/Makefile.inc
A src/mainboard/google/cyan/variants/cyan/board_info.txt
R src/mainboard/google/cyan/variants/cyan/devicetree.cb
R src/mainboard/google/cyan/variants/cyan/gpio.c
A src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl
A src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl
R src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h
R src/mainboard/google/cyan/variants/cyan/spd.c
21 files changed, 380 insertions(+), 267 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/21126/1
diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index fdeac63..ea8047f 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -1,7 +1,5 @@
-if BOARD_GOOGLE_CYAN
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
+config BOARD_GOOGLE_BASEBOARD_CYAN
+ def_bool n
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_MEC
@@ -14,6 +12,8 @@
select SOC_INTEL_BRASWELL
select HAVE_ACPI_RESUME
select PCIEXP_L1_SUB_STATE
+
+if BOARD_GOOGLE_BASEBOARD_CYAN
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
@@ -34,13 +34,21 @@
string
default google/cyan
+config VARIANT_DIR
+ string
+ default "cyan" if BOARD_GOOGLE_CYAN
+
config MAINBOARD_PART_NUMBER
string
- default "Cyan"
+ default "Cyan" if BOARD_GOOGLE_CYAN
config MAINBOARD_VENDOR
string
default "Google"
+
+config DEVICETREE
+ string
+ default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN
config VGA_BIOS_FILE
string
@@ -62,5 +70,6 @@
config GBB_HWID
string
depends on CHROMEOS
- default "CYAN TEST A-A 1829"
-endif # BOARD_GOOGLE_CYAN
+ default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN
+
+endif # BOARD_GOOGLE_BASEBOARD_CYAN
diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name
index a4562d3..91e10c9 100644
--- a/src/mainboard/google/cyan/Kconfig.name
+++ b/src/mainboard/google/cyan/Kconfig.name
@@ -1,2 +1,3 @@
config BOARD_GOOGLE_CYAN
bool "Cyan"
+ select BOARD_GOOGLE_BASEBOARD_CYAN
diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc
index 43e3c95..274e9f0 100644
--- a/src/mainboard/google/cyan/Makefile.inc
+++ b/src/mainboard/google/cyan/Makefile.inc
@@ -16,15 +16,19 @@
subdirs-y += spd
-romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
-ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c
-ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c
+ramstage-y += boardid.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += irqroute.c
ramstage-y += ramstage.c
ramstage-y += w25q64.c
-ramstage-y += boardid.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/$(VARIANT_DIR)
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl
new file mode 100644
index 0000000..9abc91e
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C2)
+{
+ /* Maxim Audio Codec */
+ Device (MAXM) /* Audio Codec driver I2C */
+ {
+ Name (_ADR, 0)
+ Name (_HID, AUDIO_CODEC_HID)
+ Name (_CID, AUDIO_CODEC_CID)
+ Name (_DDN, AUDIO_CODEC_DDN)
+ Name (_UID, 1)
+
+ /* Add DT style bindings with _DSD */
+ Name (_DSD, Package () {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ /* set maxim micbias to 2.8v */
+ Package () { "maxim,micbias", 3 },
+ }
+ })
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(SBUF,ResourceTemplate ()
+ {
+ I2CSerialBus(
+ AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */
+ ControllerInitiated, /* SlaveMode: default to ControllerInitiated */
+ 400000, /* ConnectionSpeed: in Hz */
+ AddressingMode7Bit, /* Addressing Mode: default to 7 bit */
+ "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */
+ )
+
+ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+ "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
+ } )
+ Return (SBUF)
+ }
+
+ Method (_STA)
+ {
+ If (LEqual (\S2EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+ Device (TISW) /* TI Switch driver I2C */
+ {
+ Name (_ADR, 0)
+ Name (_HID, TI_SWITCH_HID)
+ Name (_CID, TI_SWITCH_CID)
+ Name (_DDN, TI_SWITCH_DDN)
+ Name (_UID, 1)
+
+ /* Add DT style bindings with _DSD */
+ Name (_DSD, Package () {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ /* set ti micbias to 2.8v */
+ Package () { "ti,micbias", 7 },
+ }
+ })
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(SBUF,ResourceTemplate ()
+ {
+ I2CSerialBus(
+ TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */
+ ControllerInitiated, /* SlaveMode: default to ControllerInitiated */
+ 400000, /* ConnectionSpeed: in Hz */
+ AddressingMode7Bit, /* Addressing Mode: default to 7 bit */
+ "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */
+ )
+
+ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+ "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX }
+
+ } )
+ Return (SBUF)
+ }
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+ }
+}
+
+
+Scope (\_SB.PCI0.LPEA)
+{
+ Name (GBUF, ResourceTemplate ()
+ {
+ /* Jack Detect (index 0) */
+ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+ "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
+ })
+}
diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl
index 95b6951..6407a56 100644
--- a/src/mainboard/google/cyan/acpi/dptf.asl
+++ b/src/mainboard/google/cyan/acpi/dptf.asl
@@ -14,63 +14,8 @@
* GNU General Public License for more details.
*/
-#define DPTF_TSR0_SENSOR_ID 0
-#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
-#define DPTF_TSR0_PASSIVE 49
-#define DPTF_TSR0_CRITICAL 75
+/* Include Variant DPTF */
+#include <variant/acpi/dptf.asl>
-#define DPTF_TSR1_SENSOR_ID 1
-#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
-#define DPTF_TSR1_PASSIVE 65
-#define DPTF_TSR1_CRITICAL 85
-
-#define DPTF_TSR2_SENSOR_ID 2
-#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
-#define DPTF_TSR2_PASSIVE 49
-#define DPTF_TSR2_CRITICAL 75
-
-#define DPTF_ENABLE_CHARGER
-
-/* Charger performance states, board-specific values from charger and EC */
-Name (CHPS, Package () {
- Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */
- Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */
- Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
- Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */
- Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
-})
-
-/* Mainboard specific _PDL is 1GHz */
-Name (MPDL, 8)
-
-Name (DTRT, Package () {
- /* CPU Throttle Effect on CPU */
- Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
-
- /* CPU Effect on Temp Sensor 0 */
- Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
- 0x2, /* Revision */
- Package () { /* Power Limit 1 */
- 0, /* PowerLimitIndex, 0 for Power Limit 1 */
- 2000, /* PowerLimitMinimum */
- 6200, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 200 /* StepSize */
- },
- Package () { /* Power Limit 2 */
- 1, /* PowerLimitIndex, 1 for Power Limit 2 */
- 8000, /* PowerLimitMinimum */
- 8000, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 1000 /* StepSize */
- }
-})
-
-/* Include DPTF */
+/* Include SoC DPTF */
#include <acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl
index 7a4b0ea..3228a31 100644
--- a/src/mainboard/google/cyan/acpi/mainboard.asl
+++ b/src/mainboard/google/cyan/acpi/mainboard.asl
@@ -15,7 +15,7 @@
* GNU General Public License for more details.
*/
-#include <onboard.h>
+#include <variant/onboard.h>
Scope (\_SB)
{
@@ -24,189 +24,6 @@
Name (_HID, EisaId ("PNP0C0C"))
Name (_UID, 1)
}
-}
-
-Scope (\_SB.PCI0.I2C1)
-{
- Device (ETSA)
- {
- Name (_HID, "ELAN0001")
- Name (_DDN, "Elan Touchscreen ")
- Name (_UID, 5)
- Name (ISTP, 0) /* TouchScreen */
-
- Method(_CRS, 0x0, NotSerialized)
- {
- Name(BUF0,ResourceTemplate ()
- {
- I2CSerialBus(
- 0x10, /* SlaveAddress */
- ControllerInitiated, /* SlaveMode */
- 400000, /* ConnectionSpeed */
- AddressingMode7Bit, /* AddressingMode */
- "\\_SB.PCI0.I2C1", /* ResourceSource */
- )
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- BOARD_TOUCH_IRQ
- }
-
- } )
- Return (BUF0)
- }
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
-
- /* Allow device to power off in S0 */
- Name (_S0W, 4)
- }
-}
-
-Scope (\_SB.PCI0.I2C2)
-{
- /* Maxim Audio Codec */
- Device (MAXM) /* Audio Codec driver I2C */
- {
- Name (_ADR, 0)
- Name (_HID, AUDIO_CODEC_HID)
- Name (_CID, AUDIO_CODEC_CID)
- Name (_DDN, AUDIO_CODEC_DDN)
- Name (_UID, 1)
-
- /* Add DT style bindings with _DSD */
- Name (_DSD, Package () {
- ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- /* set maxim micbias to 2.8v */
- Package () { "maxim,micbias", 3 },
- }
- })
-
- Method(_CRS, 0x0, NotSerialized)
- {
- Name(SBUF,ResourceTemplate ()
- {
- I2CSerialBus(
- AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */
- ControllerInitiated, /* SlaveMode: default to ControllerInitiated */
- 400000, /* ConnectionSpeed: in Hz */
- AddressingMode7Bit, /* Addressing Mode: default to 7 bit */
- "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */
- )
-
- GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
- "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
- } )
- Return (SBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S2EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
- }
- Device (TISW) /* TI Switch driver I2C */
- {
- Name (_ADR, 0)
- Name (_HID, TI_SWITCH_HID)
- Name (_CID, TI_SWITCH_CID)
- Name (_DDN, TI_SWITCH_DDN)
- Name (_UID, 1)
-
- /* Add DT style bindings with _DSD */
- Name (_DSD, Package () {
- ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- /* set ti micbias to 2.8v */
- Package () { "ti,micbias", 7 },
- }
- })
-
- Method(_CRS, 0x0, NotSerialized)
- {
- Name(SBUF,ResourceTemplate ()
- {
- I2CSerialBus(
- TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */
- ControllerInitiated, /* SlaveMode: default to ControllerInitiated */
- 400000, /* ConnectionSpeed: in Hz */
- AddressingMode7Bit, /* Addressing Mode: default to 7 bit */
- "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */
- )
-
- GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
- "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX }
-
- } )
- Return (SBUF)
- }
-
- Method (_STA)
- {
- Return (0xF)
- }
- }
-}
-
-Scope (\_SB.PCI0.I2C6)
-{
- Device (ETPA)
- {
- Name (_HID, "ELAN0000")
- Name (_DDN, "Elan Touchpad")
- Name (_UID, 3)
- Name (ISTP, 1) /* Touchpad */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x15, /* SlaveAddress */
- ControllerInitiated, /* SlaveMode */
- 400000, /* ConnectionSpeed */
- AddressingMode7Bit, /* AddressingMode */
- "\\_SB.PCI0.I2C6", /* ResourceSource */
- )
- GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
- "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX }
- })
-
- Method (_STA)
- {
- If (LEqual (\S6EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
-
- /* Allow device to power off in S0 */
- Name (_S0W, 4)
- }
-}
-
-Scope (\_SB.PCI0.LPEA)
-{
- Name (GBUF, ResourceTemplate ()
- {
- /* Jack Detect (index 0) */
- GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
- "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
- })
}
Scope (\_SB.GPNC)
@@ -225,3 +42,6 @@
{
}
}
+
+/* Variant-specific I2C devices */
+#include <variant/acpi/mainboard.asl>
diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl
index 34ae348..1962f22 100644
--- a/src/mainboard/google/cyan/acpi/superio.asl
+++ b/src/mainboard/google/cyan/acpi/superio.asl
@@ -16,7 +16,7 @@
/* mainboard configuration */
#include <ec.h>
-#include <onboard.h>
+#include <variant/onboard.h>
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl
new file mode 100644
index 0000000..7100120
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C1)
+{
+ Device (ETSA)
+ {
+ Name (_HID, "ELAN0001")
+ Name (_DDN, "Elan Touchscreen ")
+ Name (_UID, 5)
+ Name (ISTP, 0) /* TouchScreen */
+
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(BUF0,ResourceTemplate ()
+ {
+ I2CSerialBus(
+ 0x10, /* SlaveAddress */
+ ControllerInitiated, /* SlaveMode */
+ 400000, /* ConnectionSpeed */
+ AddressingMode7Bit, /* AddressingMode */
+ "\\_SB.PCI0.I2C1", /* ResourceSource */
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ BOARD_TOUCH_IRQ
+ }
+
+ } )
+ Return (BUF0)
+ }
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl
new file mode 100644
index 0000000..f89e1bc
--- /dev/null
+++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C6)
+{
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 3)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x15, /* SlaveAddress */
+ ControllerInitiated, /* SlaveMode */
+ 400000, /* ConnectionSpeed */
+ AddressingMode7Bit, /* AddressingMode */
+ "\\_SB.PCI0.I2C6", /* ResourceSource */
+ )
+ GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,,
+ "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S6EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
diff --git a/src/mainboard/google/cyan/board_info.txt b/src/mainboard/google/cyan/board_info.txt
index 8815b36..98f3d76 100644
--- a/src/mainboard/google/cyan/board_info.txt
+++ b/src/mainboard/google/cyan/board_info.txt
@@ -1,5 +1,5 @@
Vendor name: Google
-Board name: Cyan Braswell reference board
+Board name: Cyan Braswell baseboard
Category: laptop
ROM protocol: SPI
ROM socketed: n
diff --git a/src/mainboard/google/cyan/boardid.c b/src/mainboard/google/cyan/boardid.c
index 15d26dc..0d47c43 100644
--- a/src/mainboard/google/cyan/boardid.c
+++ b/src/mainboard/google/cyan/boardid.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright(C) 2013 Google Inc.
+ * Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c
index e247c98..026a68d 100644
--- a/src/mainboard/google/cyan/ramstage.c
+++ b/src/mainboard/google/cyan/ramstage.c
@@ -15,7 +15,7 @@
#include <soc/ramstage.h>
#include <boardid.h>
-#include "onboard.h"
+#include <variant/onboard.h>
void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
{
diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c
index 98e4873..75c1890 100644
--- a/src/mainboard/google/cyan/smihandler.c
+++ b/src/mainboard/google/cyan/smihandler.c
@@ -25,7 +25,7 @@
#include <soc/pm.h>
#include <soc/gpio.h>
-#include "onboard.h"
+#include <variant/onboard.h>
/* The wake gpio is SUS_GPIO[0]. */
#define WAKE_GPIO_EN SUS_GPIO_EN0
diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc
similarity index 100%
rename from src/mainboard/google/cyan/spd/Makefile.inc
rename to src/mainboard/google/cyan/variants/cyan/Makefile.inc
diff --git a/src/mainboard/google/cyan/variants/cyan/board_info.txt b/src/mainboard/google/cyan/variants/cyan/board_info.txt
new file mode 100644
index 0000000..b1138ca
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/cyan/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Cyan
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/variants/cyan/devicetree.cb
similarity index 100%
rename from src/mainboard/google/cyan/devicetree.cb
rename to src/mainboard/google/cyan/variants/cyan/devicetree.cb
diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c
similarity index 99%
rename from src/mainboard/google/cyan/gpio.c
rename to src/mainboard/google/cyan/variants/cyan/gpio.c
index 9f9a3ae..bb7a148 100644
--- a/src/mainboard/google/cyan/gpio.c
+++ b/src/mainboard/google/cyan/variants/cyan/gpio.c
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-#include "irqroute.h"
+#include <mainboard/google/cyan/irqroute.h>
#include <soc/gpio.h>
#include <stdlib.h>
diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..f0550ee
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2105 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
+#define DPTF_TSR0_PASSIVE 49
+#define DPTF_TSR0_CRITICAL 75
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE 65
+#define DPTF_TSR1_CRITICAL 85
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE 49
+#define DPTF_TSR2_CRITICAL 75
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */
+ Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 2000, /* PowerLimitMinimum */
+ 6200, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 8000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000..194a4a1
--- /dev/null
+++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Matt DeVillier
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan touchscreen */
+#include <mainboard/google/cyan/acpi/touchscreen_elan.asl>
+
+/* Elan trackpad */
+#include <mainboard/google/cyan/acpi/trackpad_elan.asl>
+
+/* Maxim audio codec */
+#include <mainboard/google/cyan/acpi/codec_maxim.asl>
diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h
similarity index 89%
rename from src/mainboard/google/cyan/onboard.h
rename to src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h
index 5338b0c..ee826b9 100644
--- a/src/mainboard/google/cyan/onboard.h
+++ b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h
@@ -17,7 +17,7 @@
#ifndef ONBOARD_H
#define ONBOARD_H
-#include "irqroute.h"
+#include <mainboard/google/cyan/irqroute.h>
/*
* Calculation of gpio based irq.
@@ -57,7 +57,7 @@
#define BOARD_TOUCHSCREEN_NAME "touchscreen"
#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
#define BOARD_TOUCHSCREEN_I2C_BUS 0
-#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
/* SD CARD gpio */
@@ -68,12 +68,12 @@
#define AUDIO_CODEC_DDN "Maxim 98090 Codec "
#define AUDIO_CODEC_I2C_ADDR 0x10
-#define TI_SWITCH_HID "104C227E"
-#define TI_SWITCH_CID "104C227E"
-#define TI_SWITCH_DDN "TI SWITCH "
+#define TI_SWITCH_HID "104C227E"
+#define TI_SWITCH_CID "104C227E"
+#define TI_SWITCH_DDN "TI SWITCH "
#define TI_SWITCH_I2C_ADDR 0x3B
-
-#endif
#define DPTF_CPU_PASSIVE 88
#define DPTF_CPU_CRITICAL 90
+
+#endif
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/variants/cyan/spd.c
similarity index 100%
rename from src/mainboard/google/cyan/spd/spd.c
rename to src/mainboard/google/cyan/variants/cyan/spd.c
--
To view, visit https://review.coreboot.org/21126
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Gerrit-Change-Number: 21126
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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