[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable power button SMI when jumping to payload

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/21082


Change subject: soc/intel/skylake: Enable power button SMI when jumping to payload
......................................................................

soc/intel/skylake: Enable power button SMI when jumping to payload

Instead of enabling power button SMI unconditionally, add a boot state
handler to enable power button SMI just before jumping to
payload. This ensures that:
1. We do not respond to power button SMI until we know that coreboot
is done.
2. On resume, there is no need to enable power button SMI. This avoids
any power button presses during resume path from triggering a
shutdown.

BUG=b:64811381

Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/pmutil.c
M src/soc/intel/skylake/smi.c
M src/soc/intel/skylake/smihandler.c
4 files changed, 25 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/21082/1

diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 67b1f43..73e1e0e 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -160,6 +160,7 @@
 uint16_t clear_pm1_status(void);
 void enable_pm1(uint16_t events);
 uint32_t clear_smi_status(void);
+uint16_t read_pm1_enable(void);
 
 /* SMI */
 void enable_smi(uint32_t mask);
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 9b38531..b3496c3 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -136,12 +136,22 @@
 	return print_pm1_status(reset_pm1_status());
 }
 
-/* Set the PM1 register to events */
+/*
+ * Enable supplied events in PM1_EN register. This does not disable any already
+ * set events.
+ */
 void enable_pm1(u16 events)
 {
-	outw(events, ACPI_BASE_ADDRESS + PM1_EN);
+	u16 pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
+	pm1_en |= events;
+	outw(pm1_en, ACPI_BASE_ADDRESS + PM1_EN);
 }
 
+/* Read events set in PM1_EN register. */
+uint16_t read_pm1_enable(void)
+{
+	return inw(ACPI_BASE_ADDRESS + PM1_EN);
+}
 
 /*
  * SMI
diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c
index 7343637..1c264f0 100644
--- a/src/soc/intel/skylake/smi.c
+++ b/src/soc/intel/skylake/smi.c
@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <bootstate.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <console/console.h>
@@ -53,8 +54,9 @@
 void southbridge_smm_enable_smi(void)
 {
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
+
 	/* Configure events */
-	enable_pm1(PWRBTN_EN | GBL_EN);
+	enable_pm1(GBL_EN);
 	disable_gpe(PME_B0_EN);
 
 	/*
@@ -88,3 +90,10 @@
 		  "d" (APM_CNT)
 	);
 }
+
+static void pm1_enable_pwrbtn_smi(void *unused)
+{
+	enable_pm1(PWRBTN_EN);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index d87994e..3e79065 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -343,12 +343,13 @@
 static void southbridge_smi_pm1(void)
 {
 	u16 pm1_sts = clear_pm1_status();
+	u16 pm1_en = read_pm1_enable();
 
 	/*
 	 * While OSPM is not active, poweroff immediately on a power button
 	 * event.
 	 */
-	if (pm1_sts & PWRBTN_STS) {
+	if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) {
 		/* power button pressed */
 		if (IS_ENABLED(CONFIG_ELOG_GSMI))
 			elog_add_event(ELOG_TYPE_POWER_BUTTON);

-- 
To view, visit https://review.coreboot.org/21082
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11
Gerrit-Change-Number: 21082
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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