[coreboot-gerrit] Change in coreboot[master]: soc/inte/cannonlake: Define soc_intel_cannonlake_config
Pratikkumar V Prajapati (Code Review)
gerrit at coreboot.org
Fri Aug 18 01:50:34 CEST 2017
Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21080
Change subject: soc/inte/cannonlake: Define soc_intel_cannonlake_config
......................................................................
soc/inte/cannonlake: Define soc_intel_cannonlake_config
- Populate soc_intel_cannonlake_config
- Add usb.h and vr_config.h for CannonLake
Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
---
M src/soc/intel/cannonlake/chip.h
A src/soc/intel/cannonlake/include/soc/usb.h
A src/soc/intel/cannonlake/include/soc/vr_config.h
3 files changed, 297 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/21080/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 67be85d..a3f5ffc 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -20,10 +20,200 @@
#include <intelblocks/gspi.h>
#include <stdint.h>
+#include <soc/usb.h>
+#include <soc/vr_config.h>
struct soc_intel_cannonlake_config {
+
+ /* Interrupt Routing configuration.
+ * If bit7 is 1, the interrupt is disabled. */
+ uint8_t pirqa_routing;
+ uint8_t pirqb_routing;
+ uint8_t pirqc_routing;
+ uint8_t pirqd_routing;
+ uint8_t pirqe_routing;
+ uint8_t pirqf_routing;
+ uint8_t pirqg_routing;
+ uint8_t pirqh_routing;
+
+ /* GPE configuration */
+ uint32_t gpe0_en_1; /* GPE0_EN_31_0 */
+ uint32_t gpe0_en_2; /* GPE0_EN_63_32 */
+ uint32_t gpe0_en_3; /* GPE0_EN_95_64 */
+ uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */
+
+ /* Gpio group routed to each dword of the GPE0 block. Values are
+ * of the form GPP_[A:G] or GPD. */
+ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
+ uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
+ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
+
+ /* Generic IO decode ranges */
+ uint32_t gen1_dec;
+ uint32_t gen2_dec;
+ uint32_t gen3_dec;
+ uint32_t gen4_dec;
+
+ /* Enable S0iX support */
+ int s0ix_enable;
+ /* Enable DPTF support */
+ int dptf_enable;
+
+ /* Deep SX enable for both AC and DC */
+ int deep_s3_enable;
+ int deep_s5_enable;
+
+ /*
+ * Deep Sx Configuration
+ * DSX_EN_WAKE_PIN - Enable WAKE# pin
+ * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
+ * DSX_EN_AC_PRESENT_PIN - Enable AC_PRESENT pin
+ */
+ uint32_t deep_sx_config;
+
+ /* TCC activation offset */
+ uint32_t tcc_offset;
+
+ uint64_t PlatformMemorySize;
+ uint8_t SmramMask;
+ uint8_t MrcFastBoot;
+ uint32_t TsegSize;
+ uint16_t MmioSize;
+
+ /* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz.
+ * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
+ uint16_t DdrFreqLimit;
+
+ /* SAGV Low Frequency Selections in Mhz.
+ * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
+ uint16_t FreqSaGvLow;
+
+ /* SAGV Mid Frequency Selections in Mhz.
+ * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
+ uint16_t FreqSaGvMid;
+
+ /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
+ * When enabled memory will be training at two different frequencies.
+ * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */
+ uint8_t SaGv;
+
+ /* Rank Margin Tool. 1:Enable, 0:Disable */
+ uint8_t RMT;
+
+ /* LAN controller. 1:Enable, 0:Disable */
+ uint8_t PchLanEnable;
+
+ /* USB related */
+ struct usb2_port_config usb2_ports[16];
+ struct usb3_port_config usb3_ports[10];
+ uint8_t XdciEnable;
+ uint8_t SsicPortEnable;
+
+ /* SATA related */
+ uint8_t SataEnable;
+ uint8_t SataMode;
+ uint8_t SataSalpSupport;
+ uint8_t SataPortsEnable[8];
+ uint8_t SataPortsDevSlp[8];
+
+ /* Audio related */
+ uint8_t PchHdaEnable;
+ uint8_t PchHdaDspEnable;
+
+ /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
+ uint8_t PchHdaAudioLinkHda;
+
+ /* Pcie Root Ports */
+ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
+ uint8_t PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
+ uint8_t PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
+
+ /* SMBus */
+ uint8_t SmbusEnable;
+
/* GSPI */
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+
+ /* eMMC and SD */
+ uint8_t ScsEmmcEnabled;
+ uint8_t ScsEmmcHs400Enabled;
+ uint8_t PchScsEmmcHs400TuningRequired;
+ uint8_t ScsSdCardEnabled;
+ uint8_t ScsUfsEnabled;
+
+ /* Integrated Sensor */
+ uint8_t PchIshEnable;
+
+ /* Heci related */
+ uint8_t HeciTimeouts;
+ uint8_t Heci3Enabled;
+
+ /* Gfx related */
+ uint8_t IgdDvmt50PreAlloc;
+ uint8_t PrimaryDisplay;
+ uint8_t InternalGfx;
+ uint8_t ApertureSize;
+ uint8_t SkipExtGfxScan;
+ uint8_t ScanExtGfxForLegacyOpRom;
+
+ uint32_t LogoPtr;
+ uint32_t LogoSize;
+ uint32_t GraphicsConfigPtr;
+ uint8_t Device4Enable;
+
+ uint8_t RtcLock;
+ /* GPIO IRQ Select. The valid value is 14 or 15 */
+ uint8_t GpioIrqRoute;
+ /* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
+ uint8_t SciIrqSelect;
+ /* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
+ uint8_t TcoIrqSelect;
+ uint8_t TcoIrqEnable;
+ /* Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit */
+ uint8_t PchLockDownGlobalSmi;
+ /* Enable BIOS Interface Lock Down bit to prevent writes to
+ * the Backup Control Register. */
+ uint8_t PchLockDownBiosInterface;
+ /* Enable the BIOS Lock feature and set EISS bit for the
+ * BIOS region protection. */
+ uint8_t PchLockDownBiosLock;
+ /* PCH power button override period.
+ * 000b-4s, 0001b-6s, 0010b-8s, 0011b-10s, 0100b-12s, 0101b-14s */
+ uint8_t PchPmPwrBtnOverridePeriod;
+
+ enum {
+ RESET_POWER_CYCLE_DEFAULT = 0,
+ RESET_POWER_CYCLE_1S = 1,
+ RESET_POWER_CYCLE_2S = 2,
+ RESET_POWER_CYCLE_3S = 3,
+ RESET_POWER_CYCLE_4S = 4,
+ } PmConfigPwrCycDur;
+
+ /* Determines if enable Serial IRQ. 0:Disabled, 1:Enabled */
+ uint8_t PchSirqEnable;
+ /* Serial IRQ Mode Select. 0:PchQuietMode, 1:PchContinuousMode */
+ uint8_t PchSirqMode;
+ /* Start Frame Pulse Width.
+ * Values: 0:PchSfpw4Clk, 1:PchSfpw6Clk, 2:PchSfpw8Clk */
+ uint8_t PchStartFramePulse;
+ uint8_t SkipMpInit;
+ /* VrConfig Settings for 5 domains
+ * 0 = System Agent, 1 = IA Core, 2 = Ring,
+ * 3 = GT unsliced, 4 = GT sliced */
+ struct vr_config domain_vr_config[NUM_VR_DOMAINS];
+ /* HeciEnabled decides the state of Heci1 at end of boot
+ * Setting to 0 (default) disables Heci1 and hides the device from OS */
+ uint8_t HeciEnabled;
+ /* PL2 Override value in Watts */
+ uint32_t tdp_pl2_override;
+ /* Intel Speed Shift Technology */
+ uint8_t speed_shift_enable;
+ /* Enable VR specific mailbox command
+ * 00b - no VR specific cmd sent
+ * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent
+ * 10b - VR specific cmd sent for PS4 exit issue
+ * 11b - Reserved */
+ uint8_t SendVrMbxCmd;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h
new file mode 100644
index 0000000..eac017e
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/usb.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef _SOC_USB_H_
+#define _SOC_USB_H_
+
+#include <stdint.h>
+
+struct usb2_port_config {
+ uint8_t enable;
+ uint8_t ocpin;
+ uint8_t tx_bias;
+ uint8_t tx_emp_enable;
+ uint8_t pre_emp_bias;
+ uint8_t pre_emp_bit;
+};
+
+struct usb3_port_config {
+ uint8_t enable;
+ uint8_t ocpin;
+ uint8_t tx_de_emp;
+ uint8_t tx_downscale_amp;
+};
+
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h
new file mode 100644
index 0000000..47f659a
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/vr_config.h
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* VR Settings for each domain */
+
+#ifndef _SOC_VR_CONFIG_H_
+#define _SOC_VR_CONFIG_H_
+
+#include <fsp/api.h>
+
+struct vr_config {
+
+ /* The below settings will take effect when this is set to 1
+ * for that domain. */
+ uint8_t vr_config_enable;
+
+ /* Power State X current cuttof in 1/4 Amp increments
+ * Range is 0-128A */
+ uint16_t psi1threshold;
+ uint16_t psi2threshold;
+ uint16_t psi3threshold;
+
+ /* Enable power state 3/4 for different domains */
+ uint8_t psi3enable;
+ uint8_t psi4enable;
+
+ /* Imon slope correction. Specified in 1/100 increment
+ * values. Range is 0-200. 125 = 1.25 */
+ uint8_t imon_slope;
+
+ /* Imon offset correction. Units 1/1000, Range 0-63999
+ * For an offset = 12.580, use 12580. 0 = Auto */
+ uint8_t imon_offset;
+
+ /* VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A */
+ uint16_t icc_max;
+
+ /* VR Voltage Limit. Range is 0-7999mV */
+ uint16_t voltage_limit;
+
+ /* AC and DC Loadline in 1/100 mOhms. Range is 0-6249 */
+ uint16_t ac_loadline;
+ uint16_t dc_loadline;
+};
+
+/* VrConfig Settings for 4 domains
+ * 0 = System Agent, 1 = IA Core,
+ * 2 = GT unsliced, 3 = GT sliced */
+enum vr_domain {
+ VR_SYSTEM_AGENT,
+ VR_IA_CORE,
+ VR_GT_UNSLICED,
+ VR_GT_SLICED,
+ NUM_VR_DOMAINS
+};
+
+#endif
--
To view, visit https://review.coreboot.org/21080
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa
Gerrit-Change-Number: 21080
Gerrit-PatchSet: 1
Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
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