[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add LPC and SPI lock down config option

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21068


Change subject: soc/intel/skylake: Add LPC and SPI lock down config option
......................................................................

soc/intel/skylake: Add LPC and SPI lock down config option

This patch to provide new config options to perform LPC and SPI
lock down.

Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/chip.h
1 file changed, 10 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21068/1

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index efd3566..67ccec8 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -501,6 +501,16 @@
 	 * end of POST for security concerns.
 	 */
 	u8 SpiFlashCfgLockDown;
+	/* LPC Lock Down
+	 * 1b - Coreboot to handle lockdown
+	 * 0b - FSP to handle lockdown
+	 */
+	u8 lpc_lockdown;
+	/* SPI Lock Down
+	 * 1b - Coreboot to handle lockdown
+	 * 0b - FSP to handle lockdown
+	 */
+	u8 spi_lockdown;
 };
 
 typedef struct soc_intel_skylake_config config_t;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Gerrit-Change-Number: 21068
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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