[coreboot-gerrit] Change in coreboot[master]: mb/*/*/romstage.c: Clean up targets with i82801gx
Arthur Heymans (Code Review)
gerrit at coreboot.org
Thu Aug 17 10:11:26 CEST 2017
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21065
Change subject: mb/*/*/romstage.c: Clean up targets with i82801gx
......................................................................
mb/*/*/romstage.c: Clean up targets with i82801gx
Replaces magic numbers by macros.
Remove many write to DxxIP since they were 'setting' reset default
values.
Remove some GENx_IO_DEC from ASUS P5GC-MX (was copied from another
board).
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/apple/macbook21/romstage.c
M src/mainboard/asrock/g41c-gs/romstage.c
M src/mainboard/asus/p5gc-mx/romstage.c
M src/mainboard/foxconn/g41s-k/romstage.c
M src/mainboard/getac/p470/romstage.c
M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
M src/mainboard/ibase/mb899/romstage.c
M src/mainboard/intel/d510mo/romstage.c
M src/mainboard/intel/d945gclf/romstage.c
M src/mainboard/kontron/986lcd-m/romstage.c
M src/mainboard/lenovo/t60/romstage.c
M src/mainboard/lenovo/x60/romstage.c
M src/mainboard/roda/rk886ex/romstage.c
M src/southbridge/intel/i82801gx/i82801gx.h
15 files changed, 172 insertions(+), 178 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/21065/1
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 92dfe74..2111daf 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -38,7 +38,7 @@
static void ich7_enable_lpc(void)
{
/* Enable Serial IRQ */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
/* I/O Decode Ranges
* X60: 0x0210 == 00000010 00010000
@@ -48,7 +48,7 @@
* 00 = 378h - 37Fh and 778h - 77Fh
* 10 = 3BCh - 3BEh and 7BCh - 7BEh
*/
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
/* LPC_EN--LPC I/F Enables Register
* X60: 0x1f0d == 00011111 00001101
@@ -102,7 +102,9 @@
* interface. This range is selected in the LPC_COM Decode
* Range Register (D31:F0:80h, bits 3:2).
*/
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
+ | CNF1_LPC_EN | MC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
+ | COMA_LPC_EN);
/* GEN1_DEC, LPC Interface Generic Decode Range 1
* X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001
@@ -168,18 +170,18 @@
RCBA32(0x3110) = 0x00000001;
/* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0235;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
+ RCBA16(D31IR) = 0x0232;
+ RCBA16(D30IR) = 0x3246;
+ RCBA16(D29IR) = 0x0235;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x3216;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
- RCBA32(0x3418) |= (1 << 0); /* Required. */
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
+ RCBA32(FD) |= (1 << 0); /* Required. */
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
@@ -227,7 +229,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index dd885db..73fd935 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -58,8 +58,8 @@
RCBA16(D29IR) = 0x0237;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
- RCBA8(0x31ff);
+ RCBA8(OIC) = 0x03;
+ RCBA8(OIC);
reg32 = RCBA32(GCS);
reg32 |= (1 << 5);
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index a29478c..be153be 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -107,30 +107,28 @@
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// Set COM1/COM2 decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
// Enable COM1
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
+ | KBC_LPC_EN FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
+ | COMA_LPC_EN);
// Enable SuperIO Power Management Events
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
-
- /* range 0x15e0 - 0x10ef */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x40291);
-
-
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x40291);
}
static void rcba_config(void)
{
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(0x3418) = 0x003c0061;
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
+ | FD_ACAUD | 1;
/* Enable PCIe Root Port Clock Gate */
- RCBA32(0x341c) = 0x00000001;
+ RCBA32(CG) = 0x00000001;
}
static void early_ich7_init(void)
@@ -172,7 +170,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index 2a704a3..51f5e6f 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -78,7 +78,7 @@
COMB_LPC_EN | COMA_LPC_EN);
/* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */
- pci_write_config32(LPC_DEV, 0x84, 0x003c0a01);
+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01);
}
void mainboard_romstage_entry(unsigned long bist)
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index d1552a6..97191e0 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -61,17 +61,19 @@
lpt_en = 1 << 2; // enable LPT
}
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+ | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
+ | FDD_LPC_EN| lpt_en | 1);
// Enable 0x02e0 - 0x2ff
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1);
// Enable 0x600 - 0x6ff
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601);
// Enable 0x68 - 0x6f
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069);
}
/* This box has two superios, so enabling serial becomes slightly excessive.
@@ -155,18 +157,18 @@
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
+ RCBA16(D31IR) = 0x0232;
+ RCBA16(D30IR) = 0x3246;
+ RCBA16(D29IR) = 0x0237;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x3216;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
- RCBA32(0x3418) |= (1 << 0); // Required.
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
+ RCBA32(FD) |= (1 << 0); // Required.
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
@@ -221,7 +223,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 9789d2a..ea488ef 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -68,24 +68,26 @@
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// Set COM1/COM2 decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000);
// Enable COM1
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
+ | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMA_LPC_EN);
// Enable SuperIO Power Management Events
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801);
/* LPC decode range 2: Environment Controller */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040291);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291);
}
static void rcba_config(void)
{
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(0x3418) = 0x003c0061;
+ RCBA32(FD) = 0x003c0061;
/* Enable PCIe Root Port Clock Gate */
RCBA32(0x341c) = 0x00000001;
@@ -130,7 +132,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 67d3eb1..afbcc98 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -94,13 +94,13 @@
RCBA32(0x3108) = 0x10004321;
RCBA32(0x310c) = 0x00214321;
RCBA32(0x3110) = 0x00000001;
- RCBA32(0x3140) = 0x00410032;
- RCBA32(0x3144) = 0x32100237;
- RCBA32(0x3148) = 0x00000000;
+ RCBA32(D31IR) = 0x00410032;
+ RCBA32(D29IR) = 0x32100237;
+ RCBA32(D27IR) = 0x00000000;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
- RCBA8(0x31ff);
+ RCBA8(OIC) = 0x03;
+ RCBA8(OIC);
RCBA32(0x3410) = 0x00190464;
RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
@@ -119,9 +119,9 @@
static void ich7_enable_lpc(void)
{
/* Disable Serial IRQ */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
/* Decode range */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN
| LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 7088f1d..9bacd5c 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -42,15 +42,17 @@
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// Set COM1/COM2 decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
// Enable COM1/COM2/KBD/SuperIO1+2
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
+ | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMA_LPC_EN);
// Enable HWM at 0x290
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291);
// io 0x300 decode
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);
}
/* This box has one superio
@@ -136,14 +138,14 @@
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
+ RCBA16(D31IR) = 0x0132;
+ RCBA16(D30IR) = 0x0146;
+ RCBA16(D29IR) = 0x0237;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x0146;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
@@ -188,7 +190,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 502d220..8483eeb 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -57,15 +57,14 @@
static void nm10_enable_lpc(void)
{
/* Disable Serial IRQ */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
/* Decode range */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80,
- pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x80) | 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC,
+ pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010);
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291);
}
static void rcba_config(void)
@@ -74,29 +73,18 @@
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- RCBA32(0x3108) = 0x10004321;
-
- RCBA32(0x3104) = 0x00002100;
-
- /* PCIe Interrupts */
- RCBA32(0x310c) = 0x00214321;
- /* HD Audio Interrupt */
- RCBA32(0x3110) = 0x00000001;
-
/* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
+ RCBA16(D31IR) = 0x0132;
+ RCBA16(D30IR) = 0x0146;
+ RCBA16(D29IR) = 0x0237;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x0146;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
- RCBA32(0x3418) = 0x003000e2;
- RCBA32(0x3418) |= 1;
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD
+ | FD_PATA | 1;
}
void mainboard_romstage_entry(unsigned long bist)
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index e769fc5..1e3572b 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -40,13 +40,14 @@
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// Set COM1/COM2 decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
// Enable COM1
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
+ | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
// Enable SuperIO Power Management Events
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681);
}
static void rcba_config(void)
@@ -55,26 +56,20 @@
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
/* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
+ RCBA16(D31IR) = 0x0132;
+ RCBA16(D30IR) = 0x0146;
+ RCBA16(D29IR) = 0x0237;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x0146;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
- // RCBA32(0x3418) |= (1 << 0); // Required.
- // FIXME look me up!
- RCBA32(0x3418) = 0x003204e1;
+ // FIXME devicetree disables pcie3 not 2.
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE2 | (1 << 10) | FD_INTLAN
+ | FD_ACMOD | FD_ACAUD | 1;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
@@ -119,7 +114,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 3b3ff66..b03982f 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -40,24 +40,22 @@
static void ich7_enable_lpc(void)
{
- int lpt_en = 0;
- if (read_option(lpt, 0) != 0) {
- lpt_en = 1 << 2; /* enable LPT */
- }
/* Enable Serial IRQ */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
/* Set COM1/COM2 decode range */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
/* Enable COM1/COM2/KBD/SuperIO1+2 */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
+ | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMA_LPC_EN);
/* Enable HWM at 0xa00 */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);
/* COM3 decode */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9);
/* COM4 decode */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9);
/* io 0x300 decode */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);
}
/* TODO: superio code should really not be in mainboard */
@@ -191,14 +189,14 @@
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x3241;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3210;
- RCBA16(0x3148) = 0x3210;
+ RCBA16(D31IR) = 0x0132;
+ RCBA16(D30IR) = 0x3241;
+ RCBA16(D29IR) = 0x0237;
+ RCBA16(D28IR) = 0x3210;
+ RCBA16(D27IR) = 0x3210;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Now, this is a bit ugly. As per PCI specification, function 0 of a
* device always has to be implemented. So disabling ethernet port 1
@@ -245,7 +243,7 @@
reg32 |= 1;
- RCBA32(0x3418) = reg32;
+ RCBA32(FD) = reg32;
/* Enable PCIe Root Port Clock Gate */
@@ -290,7 +288,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 80b989f..3feb670 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -41,11 +41,13 @@
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN
+ | LPT_LPC_EN | COMA_LPC_EN);
/* range 0x1600 - 0x167f */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
@@ -92,18 +94,18 @@
RCBA32(0x3110) = 0x00000002;
/* dev irq route register */
- RCBA16(0x3140) = 0x1007;
- RCBA16(0x3142) = 0x0076;
- RCBA16(0x3144) = 0x3210;
- RCBA16(0x3146) = 0x7654;
- RCBA16(0x3148) = 0x0010;
+ RCBA16(D31IR) = 0x1007;
+ RCBA16(D30IR) = 0x0076;
+ RCBA16(D29IR) = 0x3210;
+ RCBA16(D28IR) = 0x7654;
+ RCBA16(D27IR) = 0x0010;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
- RCBA32(0x3418) |= (1 << 0); // Required.
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
+ RCBA32(FD) |= (1 << 0); // Required.
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
@@ -153,7 +155,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index eddb150..b59c570 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -41,12 +41,13 @@
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
-
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN
+ | LPT_LPC_EN | COMA_LPC_EN);
/* range 0x1600 - 0x167f */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c);
@@ -92,18 +93,18 @@
RCBA32(0x3110) = 0x00000002;
/* dev irq route register */
- RCBA16(0x3140) = 0x1007;
- RCBA16(0x3142) = 0x0076;
- RCBA16(0x3144) = 0x3210;
- RCBA16(0x3146) = 0x7654;
- RCBA16(0x3148) = 0x0010;
+ RCBA16(D31IR) = 0x1007;
+ RCBA16(D30IR) = 0x0076;
+ RCBA16(D29IR) = 0x3210;
+ RCBA16(D28IR) = 0x7654;
+ RCBA16(D27IR) = 0x0010;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
- RCBA32(0x3418) |= (1 << 0); // Required.
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
+ RCBA32(FD) |= (1 << 0); // Required.
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
@@ -153,7 +154,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index a488488..372042d 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -40,21 +40,22 @@
{
int lpt_en = 0;
if (read_option(lpt, 0) != 0) {
- lpt_en = 1 << 2; /* enable LPT */
+ lpt_en = LPC_LPT_EN; /* enable LPT */
}
/* Enable Serial IRQ */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
/* decode range */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
/* decode range */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+ | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
+ | FDD_LPC_EN| lpt_en | 1);
/* Enable 0x02e0 */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x1c02e1);
/* COM3 decode */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601);
/* COM4 decode */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069);
}
/* This box has two superios, so enabling serial becomes slightly excessive.
@@ -121,24 +122,22 @@
/* Set up virtual channel 0 */
/* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042220;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
+ RCBA32(D31IP) = 0x00042220;
/* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
+ RCBA16(D31IR) = 0x0232;
+ RCBA16(D30IR) = 0x3246;
+ RCBA16(D29IR) = 0x0237;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x3216;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
- RCBA32(0x3418) |= (1 << 0); /* Required. */
+ RCBA32(FD) |= (1 << 0); /* Required. */
/* This should probably go into the ACPI OS Init trap */
@@ -190,7 +189,7 @@
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index b3c1b48..df744fc 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -125,6 +125,11 @@
#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
+#define GEN1_DEC 0x84
+#define GEN2_DEC 0x88
+#define GEN3_DEC 0x8c
+#define GEN4_DEC 0x90
+
/* PCI Configuration Space (D31:F1): IDE */
#define INTR_LN 0x3c
#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
--
To view, visit https://review.coreboot.org/21065
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Gerrit-Change-Number: 21065
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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