[coreboot-gerrit] Change in coreboot[master]: amd/pi/hudson: Expand 48MHz for both osc signals

[John E. Kabat (Code Review)]

Hello Marshall Dawson,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/21034

to review the following change.


Change subject: amd/pi/hudson: Expand 48MHz for both osc signals
......................................................................

amd/pi/hudson: Expand 48MHz for both osc signals

There are typically two configurable oscillator outputs available
on APUs or FCHs.  Convert the enable function to allow either one.

Change-Id: Iaee093d05fa712f62052a3787e56c5eaf4045483
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/mainboard/pcengines/apu2/romstage.c
M src/southbridge/amd/pi/hudson/early_setup.c
M src/southbridge/amd/pi/hudson/hudson.h
3 files changed, 15 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/21034/1

diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 1ccf7c4..d6ca3a4 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -59,7 +59,7 @@
 		post_code(0x30);
 		early_lpc_init();
 
-		hudson_clk_output_48Mhz();
+		hudson_clk_output_48Mhz(1);
 		post_code(0x31);
 		console_init();
 	}
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index ae8b406..a16b84e 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -258,18 +258,26 @@
 	return nvram_pos;
 }
 
-void hudson_clk_output_48Mhz(void)
+void hudson_clk_output_48Mhz(u32 osc)
 {
 	u32 ctrl;
 
 	/*
-	 * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
-	 * 48Mhz will be on ball AP13 (FT3b package)
+	 * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M)
+	 * or OSCOUT2 (USBCLK/25M_48M_OSC).  The frequency defaults to 48 MHz.
 	 */
 	ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));
 
-	/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
-	ctrl &= (u32)~(1<<2);
+	switch (osc) {
+	case 1:
+		ctrl &= (u32)~(1 << 2);
+		break;
+	case 2:
+		ctrl &= (u32)~(1 << 7);
+		break;
+	default:
+		return; /* do nothing if invalid */
+	}
 	write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);
 }
 
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 2ccd485..cbf1e1f 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -182,7 +182,7 @@
 void hudson_lpc_port80(void);
 void hudson_lpc_decode(void);
 void hudson_pci_port80(void);
-void hudson_clk_output_48Mhz(void);
+void hudson_clk_output_48Mhz(u32 osc);
 void hudson_read_mode(u32 mode);
 void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
 void hudson_disable_4dw_burst(void);

-- 
To view, visit https://review.coreboot.org/21034
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iaee093d05fa712f62052a3787e56c5eaf4045483
Gerrit-Change-Number: 21034
Gerrit-PatchSet: 1
Gerrit-Owner: John E. Kabat <sljkrr at gmail.com>
Gerrit-Reviewer: John E. Kabat Jr. <john.kabat at scarletltd.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
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