[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Move LPC lock down config after PCI enumeration

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21000


Change subject: soc/intel/skylake: Move LPC lock down config after PCI enumeration
......................................................................

soc/intel/skylake: Move LPC lock down config after PCI enumeration

This patch to ensure that coreboot is meeting Intel Silicon
recommendation to performing register lockdown.

TEST=Ensure LPC register 0xDC bit 1 and 7 is set.

Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/finalize.c
A src/soc/intel/skylake/lockdown.c
3 files changed, 69 insertions(+), 24 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/21000/1

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index baf6f01..7046b81 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -53,6 +53,7 @@
 ramstage-y += i2c.c
 ramstage-y += igd.c
 ramstage-y += irq.c
+ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += me.c
 ramstage-y += memmap.c
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 34f26eb..01aa4dd 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -167,12 +167,6 @@
 
 	/* Bios Interface Lock */
 	if (config->LockDownConfigBiosInterface == 0) {
-		pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
-				  pci_read_config8(PCH_DEV_LPC,
-						   BIOS_CNTL) | LPC_BC_BILD);
-		/* Reads back for posted write to take effect */
-		pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
-
 		fast_spi_set_bios_interface_lock_down();
 
 		/* GCS reg of DMI */
@@ -180,28 +174,12 @@
 	}
 
 	/* Bios Lock */
-	if (config->LockDownConfigBiosLock == 0) {
-		pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
-				  pci_read_config8(PCH_DEV_LPC,
-						   BIOS_CNTL) | LPC_BC_LE);
-
-		/* Ensure an additional read back after performing lock down */
-		pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
-
+	if (config->LockDownConfigBiosLock == 0)
 		fast_spi_set_lock_enable();
-	}
 
 	/* SPIEiss */
-	if (config->LockDownConfigSpiEiss == 0) {
-		pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
-				  pci_read_config8(PCH_DEV_LPC,
-						   BIOS_CNTL) | LPC_BC_EISS);
-
-		/* Ensure an additional read back after performing lock down */
-		pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
-
+	if (config->LockDownConfigSpiEiss == 0)
 		fast_spi_set_eiss();
-	}
 }
 
 static void soc_finalize(void *unused)
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
new file mode 100644
index 0000000..f554b8a
--- /dev/null
+++ b/src/soc/intel/skylake/lockdown.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <bootstate.h>
+#include <chip.h>
+#include <console/console.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <string.h>
+
+static void lpc_lockdown_config(void)
+{
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct soc_intel_skylake_config *config = dev->chip_info;
+
+	/* Bios Interface Lock */
+	if (config->LockDownConfigBiosInterface == 0) {
+		pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
+				  pci_read_config8(PCH_DEV_LPC,
+						   BIOS_CNTL) | LPC_BC_BILD);
+		/* Reads back for posted write to take effect */
+		pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
+	}
+
+	/* Bios Lock */
+	if (config->LockDownConfigBiosLock == 0) {
+		pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
+				  pci_read_config8(PCH_DEV_LPC,
+						   BIOS_CNTL) | LPC_BC_LE);
+
+		/* Ensure an additional read back after performing lock down */
+		pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
+	}
+
+	/* SPIEiss */
+	if (config->LockDownConfigSpiEiss == 0) {
+		pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
+				  pci_read_config8(PCH_DEV_LPC,
+						   BIOS_CNTL) | LPC_BC_EISS);
+
+		/* Ensure an additional read back after performing lock down */
+		pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
+	}
+}
+
+static void platform_lockdown_config(void *unused)
+{
+	/* LPC lock down configuration */
+	lpc_lockdown_config();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
+						NULL);
\ No newline at end of file

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee
Gerrit-Change-Number: 21000
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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