[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Fix booting with FSB800 DDR667 combination
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sun Aug 13 16:05:06 CEST 2017
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20981
Change subject: nb/intel/x4x: Fix booting with FSB800 DDR667 combination
......................................................................
nb/intel/x4x: Fix booting with FSB800 DDR667 combination
A small typo in the dll setting code prevented this combination from
booting.
TESTED on ga-g41m-es2l with 800MHz FSB CPU and 667MHz ddr2
Change-Id: Ib013471773c20336ba0902b7f328bfb6ef970747
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/x4x/raminit_ddr2.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/20981/1
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index bc012d2..f9a8c40 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -932,7 +932,7 @@
if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) &&
(s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {
- i = MCHBAR8(0x180) & 0xf;
+ i = MCHBAR8(0x1c8) & 0xf;
i = (i + 10) % 14;
MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;
MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;
--
To view, visit https://review.coreboot.org/20981
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib013471773c20336ba0902b7f328bfb6ef970747
Gerrit-Change-Number: 20981
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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