[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Revert CAR teardown wbinvd

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20967


Change subject: soc/amd/stoneyridge: Revert CAR teardown wbinvd
......................................................................

soc/amd/stoneyridge: Revert CAR teardown wbinvd

Change the cache-as-ram teardown to use invd instead of wbinvd.

CAR teardown had been modified to use wbinvd to send CAR contents
to DRAM backing prior to teardown.  This allowed CAR variables,
stack, and local variables to be preserved while running the
AMD_DISABLE_STACK macro.

Using the wbinvd instruction has the side effect of sending all
dirty cache contents to DRAM and not only our CAR data.  This
would likely cause corruption, e.g. during S3 resume.

Stoney Ridge now uses a postcar stage and this is no longer a
requirement.

Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
1 file changed, 2 insertions(+), 27 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/20967/1

diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index 92fd7e2..c744e47 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -401,16 +401,6 @@
 *   Return any family specific controls to their 'standard'
 *   settings for using cache with main memory.
 *
-* Note: Customized for coreboot:
-*   A wbinvd is used to send cache to memory.  The existing stack is preserved
-*   at its original location and additional information is preserved (e.g.
-*   coreboot CAR globals, heap structures, etc.). This implementation should
-*   NOT be used with S3 resume IF the stack/cache area is not reserved and
-*   over system memory.
-*
-*   This CPU resume path doesn't use CAR, but be careful if porting to
-*   other CPUs.
-*
 * Inputs:
 *       ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
 * Outputs:
@@ -644,12 +634,7 @@
     # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
     #--------------------------------------------------------------------------
 
-    #--------------------------------------------------------------------------
-    # Send cache to memory. Preserve stack and coreboot CAR globals.
-    # This shouldn't be used with S3 resume IF the stack/cache area is
-    # not reserved and over system memory.
-    #--------------------------------------------------------------------------
-    wbinvd
+    invd
 
 #    #.if (bh == 01h) || (bh == 03h)      ; Is this TN or KM?
 #    cmp   $01, %bh
@@ -1289,17 +1274,7 @@
 .endm
 
 /*****************************************************************************
-* AMD_DISABLE_STACK:  Implementation is modified for coreboot from
-*                     the original AMD intent.  A WBINVD is used in the HOOK
-*                     to send dirty cache contents to DRAM backing before
-*                     disabling cache-as-ram.  This is not safe for S3 resume.
-*
-*                     todo:
-*                       * rework PI/AGESA source to set DRAM to UC to send
-*                         writes directly to memory
-*                       * move DCACHE_BASE or use postcar stage for teardown
-*                         to eliminate car_migrated problem that will occur
-*                         after wbinvd is changed back to invd
+* AMD_DISABLE_STACK:
 *
 *   In:
 *       none

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a
Gerrit-Change-Number: 20967
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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