[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode
Subrata Banik (Code Review)
gerrit at coreboot.org
Thu Aug 10 11:07:24 CEST 2017
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20940
Change subject: soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode
......................................................................
soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode
Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.
TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.
Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/uart.c
1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/20940/1
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index 6f5fb6d..7481c24 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -25,6 +25,12 @@
#include <soc/pcr_ids.h>
#include <soc/iomap.h>
+/* Serial IO UART controller legacy mode */
+#define PCR_SERIAL_IO_GPPRVRW7 0x618
+#define PCR_SIO_PCH_LEGACY_UART0 (1 << 0)
+#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1)
+#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2)
+
/* Clock divider parameters for 115200 baud rate */
#define CLK_M_VAL 0x30
#define CLK_N_VAL 0xc35
@@ -57,6 +63,19 @@
base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
uart_common_init(p->dev, base, CLK_M_VAL, CLK_N_VAL);
+
+ /* Put UART2 in byte access mode for 16550 compatibility */
+ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
+ pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
+ PCR_SIO_PCH_LEGACY_UART2);
+
+ /*
+ * Dummy read after setting any of GPPRVRW7.
+ * Required for UART 16550 8-bit Legacy mode to become active
+ */
+ lpss_clk_read(base);
+ }
+
gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
}
--
To view, visit https://review.coreboot.org/20940
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48
Gerrit-Change-Number: 20940
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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