[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add proper support to enable UART2 in 16550 mode

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20939


Change subject: soc/intel/skylake: Add proper support to enable UART2 in 16550 mode
......................................................................

soc/intel/skylake: Add proper support to enable UART2 in 16550 mode

Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.

TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.

Change-Id: I5f23fef4522743efd49167afb04d56032e16e417
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/bootblock/uart.c
1 file changed, 8 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20939/1

diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
index 26b81c0..36fac36 100644
--- a/src/soc/intel/skylake/bootblock/uart.c
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -48,9 +48,16 @@
 	uart_common_init(PCH_DEV_UART2, base, CLK_M_VAL, CLK_N_VAL);
 
 	/* Put UART2 in byte access mode for 16550 compatibility */
-	if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
+	if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
 		pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
 			PCR_SIO_PCH_LEGACY_UART2);
 
+		/*
+		 * Dummy read after setting any of GPPRVRW7.
+		 * Required for UART 16550 8-bit Legacy mode to become active
+		 */
+		lpss_clk_read(base);
+	}
+
 	gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5f23fef4522743efd49167afb04d56032e16e417
Gerrit-Change-Number: 20939
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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