[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add missing _PCH_DEV definitions

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20932


Change subject: soc/intel/cannonlake: Add missing _PCH_DEV definitions
......................................................................

soc/intel/cannonlake: Add missing _PCH_DEV definitions

Add all missing _PCH_DEV definitions to pci_devs.h

Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/cannonlake/include/soc/pci_devs.h
1 file changed, 15 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/20932/1

diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index f687a33..d2f35af 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -53,9 +53,13 @@
 #define  PCH_DEVFN_THERMAL		_PCH_DEVFN(THERMAL, 0)
 #define  PCH_DEVFN_UFS		_PCH_DEVFN(THERMAL, 5)
 #define  PCH_DEVFN_GSPI2		_PCH_DEVFN(THERMAL, 6)
+#define  PCH_DEV_THERMAL		_PCH_DEV(THERMAL, 0)
+#define  PCH_DEV_UFS		_PCH_DEV(THERMAL, 5)
+#define  PCH_DEV_GSPI2		_PCH_DEV(THERMAL, 6)
 
 #define PCH_DEV_SLOT_ISH	0x13
 #define  PCH_DEVFN_ISH		_PCH_DEVFN(ISH, 0)
+#define  PCH_DEV_ISH		_PCH_DEV(ISH, 0)
 
 #define PCH_DEV_SLOT_XHCI	0x14
 #define  PCH_DEVFN_XHCI		_PCH_DEVFN(XHCI, 0)
@@ -102,8 +106,10 @@
 #define  PCH_DEV_I2C4		_PCH_DEV(SIO2, 0)
 #define  PCH_DEV_I2C5		_PCH_DEV(SIO2, 1)
 #define  PCH_DEV_UART2		_PCH_DEV(SIO2, 2)
+
 #define PCH_DEV_SLOT_STORAGE	0x1A
 #define  PCH_DEVFN_EMMC	_PCH_DEVFN(STORAGE, 0)
+#define  PCH_DEV_EMMC		_PCH_DEV(STORAGE, 0)
 
 #define PCH_DEV_SLOT_PCIE	0x1c
 #define  PCH_DEVFN_PCIE1	_PCH_DEVFN(PCIE, 0)
@@ -120,12 +126,18 @@
 #define  PCH_DEV_PCIE4		_PCH_DEV(PCIE, 3)
 #define  PCH_DEV_PCIE5		_PCH_DEV(PCIE, 4)
 #define  PCH_DEV_PCIE6		_PCH_DEV(PCIE, 5)
+#define  PCH_DEV_PCIE7		_PCH_DEV(PCIE, 6)
+#define  PCH_DEV_PCIE8		_PCH_DEV(PCIE, 7)
 
 #define PCH_DEV_SLOT_PCIE_1	0x1d
 #define  PCH_DEVFN_PCIE9	_PCH_DEVFN(PCIE_1, 0)
 #define  PCH_DEVFN_PCIE10	_PCH_DEVFN(PCIE_1, 1)
 #define  PCH_DEVFN_PCIE11	_PCH_DEVFN(PCIE_1, 2)
 #define  PCH_DEVFN_PCIE12	_PCH_DEVFN(PCIE_1, 3)
+#define  PCH_DEV_PCIE9		_PCH_DEV(PCIE_1, 0)
+#define  PCH_DEV_PCIE10	_PCH_DEV(PCIE_1, 1)
+#define  PCH_DEV_PCIE11	_PCH_DEV(PCIE_1, 2)
+#define  PCH_DEV_PCIE12	_PCH_DEV(PCIE_1, 3)
 
 #define PCH_DEV_SLOT_SIO3	0x1e
 #define  PCH_DEVFN_UART0	_PCH_DEVFN(SIO3, 0)
@@ -134,6 +146,8 @@
 #define  PCH_DEVFN_GSPI1	_PCH_DEVFN(SIO3, 3)
 #define  PCH_DEV_UART0		_PCH_DEV(SIO3, 0)
 #define  PCH_DEV_UART1		_PCH_DEV(SIO3, 1)
+#define  PCH_DEV_GSPI0		_PCH_DEV(SIO3, 2)
+#define  PCH_DEV_GSPI1		_PCH_DEV(SIO3, 3)
 
 #define PCH_DEV_SLOT_LPC	0x1f
 #define  PCH_DEVFN_LPC		_PCH_DEVFN(LPC, 0)
@@ -151,6 +165,7 @@
 #define  PCH_DEV_SMBUS		_PCH_DEV(LPC, 4)
 #define  PCH_DEV_SPI		_PCH_DEV(LPC, 5)
 #define  PCH_DEV_GBE		_PCH_DEV(LPC, 6)
+#define  PCH_DEV_TRACEHUB	_PCH_DEV(LPC, 7)
 
 static inline int spi_devfn_to_bus(unsigned int devfn)
 {

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3
Gerrit-Change-Number: 20932
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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