[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/earlyinit: Add Kconfig for PCIe Gen3

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20929


Change subject: nb/intel/sandybridge/earlyinit: Add Kconfig for PCIe Gen3
......................................................................

nb/intel/sandybridge/earlyinit: Add Kconfig for PCIe Gen3

Add a Kconfig option to enable PCI Gen3.
At the moment it's only supported by MRC as a special training sequence
is required, that hasn't been implemented yet.

Change-Id: I07b66cb353a3e572183ee00c79e8f240cf79107e
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
3 files changed, 17 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/20929/1

diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 2d13f28..f033a5d 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -86,6 +86,13 @@
 	  We can optimize the native case but the MRC blob requires it
 	  to be at 0xf0000000.
 
+config ENABLE_PEG_GEN3
+	def_bool n
+	depends on !USE_NATIVE_RAMINIT
+	help
+	  PCIe Gen3 needs a special training sequence that increases boot time.
+	  Native ram init doesn't support PCI Gen3 PEG ports.
+
 if USE_NATIVE_RAMINIT
 
 config DCACHE_RAM_BASE
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index a5c6ce2..6b89219 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -285,9 +285,15 @@
 	if (pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B) & (1 << 20)) {
 		printk(BIOS_DEBUG, "PEG: PCIe Gen3 disabled\n");
 		link_mask = (3 << 1);
-	} else
+	} else {
 		printk(BIOS_DEBUG, "PEG: PCIe Gen3 supported\n");
 
+		if (!IS_ENABLED(CONFIG_ENABLE_PEG_GEN3)) {
+			link_mask = (3 << 1);
+			printk(BIOS_DEBUG, "PEG: Limiting to PCIe Gen2\n");
+		}
+	}
+
 	/* Configure PEG10/PEG11/PEG12 PHY */
 	ivybridge_peg_phy();
 
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 7145841..2d53c33 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -272,6 +272,9 @@
 
 	mainboard_fill_pei_data(&pei_data);
 
+	/* Init PCIe Gen3 if requested */
+	pei_data.pcie_init = IS_ENABLED(CONFIG_ENABLE_PEG_GEN3);
+
 	post_code(0x3a);
 	pei_data.boot_mode = s3resume ? 2 : 0;
 	timestamp_add_now(TS_BEFORE_INITRAM);

-- 
To view, visit https://review.coreboot.org/20929
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I07b66cb353a3e572183ee00c79e8f240cf79107e
Gerrit-Change-Number: 20929
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170809/694f7c9f/attachment.html>