[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/early_init: Read HWSTRAP

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20927


Change subject: nb/intel/sandybridge/early_init: Read HWSTRAP
......................................................................

nb/intel/sandybridge/early_init: Read HWSTRAP

Read HWSTRAP and split the PEG port into smaller chunks if neccessary.
Limit the link width on each port and set DEVEN bits for each port.

Needs test on all platforms.

Change-Id: I61a886b20dc93384f5ea209c803a515fd06df178
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/sandybridge.h
2 files changed, 66 insertions(+), 6 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/20927/1

diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index f1d9efe..f014e80 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -85,6 +85,10 @@
 	u8 reg8;
 	u8 gfxsize;
 
+	/* Just make sure IGD is on ... */
+	reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD;
+	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
+
 	reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID);
 	switch (reg16) {
 	case 0x0102: /* GT1 Desktop */
@@ -148,6 +152,61 @@
 	reg32 = MCHBAR32(0x5418);
 	reg32 |= (1 << 4) | (1 << 5);
 	MCHBAR32(0x5418) = reg32;
+}
+
+/* PEG port split depending on HWSTRAP */
+static void peg1x_hwstrap_port_split(void)
+{
+	u32 deven;
+	u8 peg_lanes[3] = {16, 0, 0};
+
+	printk(BIOS_DEBUG, "PEG: lane configuration ");
+	switch ((pci_read_config32(PCI_DEV(0, 1, 0), HWSTRAP) >> 16) & 0x3) {
+	case 0:
+		printk(BIOS_DEBUG, "x8 x4 x4\n");
+		peg_lanes[0] = 8;
+		peg_lanes[1] = 4;
+		peg_lanes[2] = 4;
+		break;
+	case 2:
+		printk(BIOS_DEBUG, "x8 x8\n");
+		peg_lanes[0] = 8;
+		peg_lanes[1] = 8;
+		peg_lanes[2] = 0;
+		break;
+	default:
+		printk(BIOS_DEBUG, "x16\n");
+		break;
+	}
+
+	/*
+	 * The HWSTRAP configures DEVEN and sets the link width on each
+	 * PEG port. Note that the LCAP bit's are write-once !
+	 */
+	deven = pci_read_config16(PCI_DEV(0, 0, 0), DEVEN);
+	deven &= ~(DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12);
+	if (peg_lanes[0] > 0) {
+		deven |= DEVEN_PEG10;
+		u32 tmp = pci_read_config32(PCI_DEV(0, 1, 0), LCAP);
+		tmp &= ~(0x1f << 4);
+		tmp |= (peg_lanes[0] << 4);
+		pci_write_config32(PCI_DEV(0, 1, 0), LCAP, tmp);
+	}
+	if (peg_lanes[1] > 0) {
+		deven |= DEVEN_PEG11;
+		u32 tmp = pci_read_config32(PCI_DEV(0, 1, 1), LCAP);
+		tmp &= ~(0x1f << 4);
+		tmp |= (peg_lanes[1] << 4);
+		pci_write_config32(PCI_DEV(0, 1, 1), LCAP, tmp);
+	}
+	if (peg_lanes[2] > 0) {
+		deven |= DEVEN_PEG12;
+		u32 tmp = pci_read_config32(PCI_DEV(0, 1, 2), LCAP);
+		tmp &= ~(0x1f << 4);
+		tmp |= (peg_lanes[2] << 4);
+		pci_write_config32(PCI_DEV(0, 1, 2), LCAP, tmp);
+	}
+	pci_write_config16(PCI_DEV(0, 0, 0), DEVEN, deven);
 }
 
 /* Static PHY configuration for IvyBridge */
@@ -250,7 +309,6 @@
 void sandybridge_early_initialization(int chipset_type)
 {
 	u32 capid0_a;
-	u32 deven;
 	u8 reg8;
 
 	/* Device ID Override Enable should be done very early */
@@ -271,12 +329,11 @@
 	/* Setup IOMMU BARs */
 	sandybridge_init_iommu();
 
-	/* Device Enable, don't touch PEG bits */
-	deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD;
-	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven);
-
 	sandybridge_setup_graphics();
 
+	/* Read PEG HWSTRAP and configure ports */
+	peg1x_hwstrap_port_split();
+
 	/* Write magic value to start PEG link training.
 	 * This should be done in PCI device enumeration, but
 	 * the PCIe specification requires to wait at least 100msec
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 9d88c70..039e760 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -109,7 +109,10 @@
 /* Device 0:1.0 PCI configuration space (PCI Express) */
 
 #define BCTRL1		0x3e	/* 16bit */
-
+#define LCAP		0xac	/* 32bit */
+#define LCAP2		0xcc	/* 32bit */
+#define LCTL2		0xd0	/* 16bit */
+#define HWSTRAP		0x504	/* 32bit */
 
 /* Device 0:2.0 PCI configuration space (Graphics Device) */
 

-- 
To view, visit https://review.coreboot.org/20927
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I61a886b20dc93384f5ea209c803a515fd06df178
Gerrit-Change-Number: 20927
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170809/3e58ba22/attachment-0001.html>